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Scheduling parallel tasks to minimize average response time 94

Scheduling parallel tasks to minimize average response time

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Proceedings of the fifth annual acm-SIAM symposium on Discrete algorithms

作者： John Turek Uwe Schwiegelshohn Joel L. Wolf Philip S. Yu IBM T.J. Watson Research Center P.O. Box 704 Yorktown Heights NY

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PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems 57

PIM-MMU: A Memory Management Unit for Accelerating Data Tran...

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57th annual IEEE/acm International symposium on Microarchitecture, MICRO 2024

作者： Lee, Dongjae Hyun, Bongjoon Kim, Taehun Rhu, Minsoo School of Electrical Engineering KAIST Korea Republic of

ISBN: (纸本)9798350350579

Processing-in-memory (PIM) has emerged as a promising solution for accelerating memory-intensive workloads as they provide high memory bandwidth to the processing units. This approach has drawn attention not only from the academic community but also from the industry, leading to the development of real-world commercial PIM devices. In this work, we first conduct an in-depth characterization on UPMEM's general-purpose PIM system and analyze the bottlenecks caused by the data transfers across the DRAM and PIM address space. Our characterization study reveals several critical challenges associated with DRAM↔PIM data transfers in memory bus integrated PIM systems, for instance, its high CPU core utilization, high power consumption, and low read/write throughput for both DRAM and PIM. Driven by our key findings, we introduce the PIM-MMU architecture which is a hardware/software co-design that enables energy-efficient DRAM↔PIM transfers for PIM systems. PIM-MMU synergistically combines a hardware-based data copy engine, a PIM-optimized memory scheduler, and a heterogeneity-Aware memory mapping function, the utilization of which is supported by our PIM-MMU software stack, significantly improving the efficiency of DRAM↔PIM data transfers. Experimental results show that PIM-MMU improves the DRAM↔PIM data transfer throughput by an average 4.1× and enhances its energy-efficiency by 4.1×, leading to a 2.2× end-To-end speedup for real-world PIM workloads. © 2024 IEEE.

关键词： parallel architectures

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Data Access Partitioning for Fine-grain parallelism on Multicore architectures 40

Data Access Partitioning for Fine-grain Parallelism on Multi...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Michael Chu Rajiv Ravindran Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Advanced Computer Architecture Laboratory Ann Arbor MI Parallel Computing Platforms group Microsoft Corporation Ann Arbor MI Java Compilers and Tools Laboratory at Hewlett-Packard Ann Arbor MI

ISBN: (纸本)9780769530475

The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a single chip requires programmer and compiler intervention to increase the amount of parallel work possible. Much of the recent work has fallen into the areas of coarse-grain parallelization: new programming models and different ways to exploit threads and data-level parallelism. This work focuses on a complementary direction, improving performance through automated fine-grain parallelization. The main difficulty in achieving a performance benefit from fine-grain parallelism is the distribution of data memory accesses across the data caches of each core. Poor choices in the placement of data accesses can lead to increased memory stalls and low resource utilization. We propose a profile-guided method for partitioning memory accesses across distributed data caches. First, a profile determines affinity relationships between memory accesses and working set characteristics of individual memory operations in the program. Next, a program-level partitioning of the memory operations is performed to divide the memory accesses across the data caches. As a result, the data accesses are proactively dispersed to reduce memory stalls and improve computation parallelization. A final detailed partitioning of the computation instructions is performed with knowledge of the cache location of their associated data. Overall, our data partitioning reduces stall cycles by up to 51 % versus data-incognizant partitioning, and has an overall speedup average of 30% over a single core processor.

关键词： Multicore processing parallel processing Programming profession Program processors Multiprocessor interconnection networks Computer architecture parallel programming Yarn Microarchitecture Laboratories

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Compilers and parallel architectures (abstract only): sequential to parallel mapping strategies 87

Compilers and parallel architectures (abstract only): sequen...

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Proceedings of the 15th annual conference on Computer Science

作者： Roger Olmstead Dept. of Mathematics San Diego State University

ISBN: (纸本)9780897912181

The parallel optimizing compiler is offered as the only viable means of fully exploiting the power of parallel architectures and applying it to mainstream computing problems. In this context, “mainstream” includes -but should not be limited to- scientific computing, which generally implies the solving of partial differential equations, fast Fourier transforms, matrix manipulations, etc. Basically our motivation is to provide the fast execution of a broad class of *** requirements of general parallel computing are examined from an engineering perspective and architectures are evaluated in the context of accepted standards, These standards include cost, reliability/fault tolerance, and performance. To simplify the evaluation process, the standards are applied to classes rather than individual architectures. Two classes of architectures exist: algorithmically and computationally specialized architectures (e.g., systolic arrays, SIMD machines, associative processors) and computationally generalized architectures (e.g., MIMD homogeneous multiprocessors with shared central memory). As each standard is applied, generalized architectures invariably prove superior. Although some algorithmically specialized computers, (e.g., systolic arrays) are admittedly less expensive than their more generalized counterparts (though this is not the case with most SIMD machines), total system cost rapidly becomes prohibitive when one considers the vast number of possible algorithms encountered in solving mainstream computing problems. Reliability also favors the generalized machine. Clearly, a machine rich in data paths and redundancy offers superior fault tolerance. Concerning performance, while it is true that algorithmically specialized architectures can occasionally provide nearly optimal solutions to certain specific problems, generalized architectures can produce both high-throughput and rapid turnaround. Indeed, a generalized machine might make use of one or more algorithmic

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A comparision of superscalar and decoupled access/execute architectures 26

A comparision of superscalar and decoupled access/execute ar...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Matthew K. Farrens Pius Ng Phil Nico Institute of Systems Engineering Huazhong University of Science and Technology Wuhan China Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818652806

Even with a very accurate dynamic branch predictor, a superscalar processor must predict instruction fetch addresses no later than the first pipeline stage to avoid suffering pipeline bubbles every time a branch is taken. Unfortunately, branch addresses generally are not known prior to instruction decode. Therefore, some indirect technique is required to identify a branch instruction and enable branch prediction while the branch instruction is being fetched. This is the branch identification problem. Intel Pentium adopts a scheme that solves this problem; however, its scheme assumes an issue rate of two instructions per cycle. An aggressive superscalar processor, issuing more than two instructions per cycle, cannot effectively use that scheme. The authors propose and compare two viable schemes for solving the branch identification problem for wide-issue superscalar processors.< >

关键词： parallel architectures Pipeline processing Scheduling

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Minimizing randomness in minimum spanning tree, parallel connectivity, and set maxima algorithms 02

Minimizing randomness in minimum spanning tree, parallel con...

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Proceedings of the thirteenth annual acm-SIAM symposium on Discrete algorithms

作者： Seth Pettie Vijaya Ramachandran The Univ. of Texas at Austin Austin TX

ISBN: (纸本)9780898715132

There are several fundamental problems for which there are optimal randomized algorithms, but whose deterministic complexity remains unresolved. Among such problems are the minimum spanning tree problem, the set maxima problem, the problem of computing connected components and (minimum) spanning trees in parallel and the problem of performing sensitivity analysis on shortest path trees and minimum spanning trees. For each of these problems there is an optimal randomized algorithm which uses a linear number of random bits. We propose new algorithms (or adapt old ones) for these problems which preserve optimality while saving an exponential number of random bits. In the case of computing minimum spanning trees and MST/SSSP sensitivity analysis, we reduce the dependence on randomness to log* n random *** also consider the problem of selection, for which we give two algorithms which make an expected 1.5n + o(n) comparisons; one uses O(log n) random bits and is uniform, the other uses O(log log n) random bits and is non-uniform.

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MIMD synchronization on SIMT architectures 49

MIMD synchronization on SIMT architectures

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Ahmed ElTantawy Tor M. Aamodt University of British Columbia

ISBN: (纸本)9781509035090

In the single-instruction multiple-threads (SIMT) execution model, small groups of scalar threads operate in lockstep. Within each group, current SIMT hardware implementations serialize the execution of threads that follow different paths, and to ensure efficiency, revert to lockstep execution as soon as possible. These constraints must be considered when adapting algorithms that employ synchronization. A deadlock-free program on a multiple-instruction multiple-data (MIMD) architecture may deadlock on a SIMT machine. To avoid this, programmers need to restructure control flow with SIMT scheduling constraints in mind. This requires programmers to be familiar with the underlying SIMT hardware. In this paper, we propose a static analysis technique that detects SIMT deadlocks by inspecting the application control flow graph (CFG). We further propose a CFG transformation that avoids SIMT deadlocks when synchronization is local to a function. Both the analysis and the transformation algorithms are implemented as LLVM compiler passes. Finally, we propose an adaptive hardware reconvergence mechanism that supports MIMD synchronization without changing the application CFG, but which can leverage our compiler analysis to gain efficiency. The static detection has a false detection rate of only 4%-5%. The automated transformation has an average performance overhead of 8.2%-10.9% compared to manual transformation. Our hardware approach performs on par with the compiler transformation, however, it avoids synchronization scope limitations, static instruction and register overheads, and debuggability challenges that are present in the compiler only solution.

关键词： System recovery Synchronization Hardware Graphics processing units Instruction sets Manuals Programming

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WaveScalar 36

WaveScalar

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： S. Swanson K. Michelson A. Schwerin M. Oskin Computer Science and Engineering University of Washington USA

ISBN: (纸本)9780769520438

Silicon technology continues to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge. Ever increasing wire-delay relative to switching speed and the exponential cost of circuit complexity make simply scaling up existing processor designs futile. In this paper, we present an alternative to superscalar design, WaveScalar. WaveScalar is a dataflow instruction set architecture and execution model designed for scalable, low-complexity/high performance processors. WaveScalar is unique among dataflow architectures in efficiently providing traditional memory semantics. At last, a dataflow machine can run "real-world" programs, written in any language, without sacrificing parallelism. The WaveScalar ISA is designed to run on an intelligent memory system. Each instruction in a WaveScalar binary executes in place in the memory system and explicitly communicates with its dependents in dataflow fashion. WaveScalar architectures cache instructions and the values they operate on in a WaveCache, a simple grid of "alu-in-cache" nodes. By co-locating computation and data in physical space, the WaveCache minimizes long wire, high-latency communication. This paper introduces the WaveScalar instruction set and evaluates a simulated implementation based on current technology. Results for the SPEC and Mediabench applications demonstrate that the WaveCache out-performs an aggressively configured superscalar design by 2-7 times, with ample opportunities for future optimizations.

关键词： Space technology Silicon Availability Switching circuits Costs Complexity theory Process design parallel processing Instruction sets Intelligent systems

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A Framework for Analyzing Resparsification algorithms 17

A Framework for Analyzing Resparsification Algorithms

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annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Rasmus Kyng Jakub Pachocki Richard Peng Sushant Sachdeva Yale University Harvard University Georgia Tech Google

ISBN: (纸本)9781510836358

A spectral sparsifier of a graph G is a sparser graph H that approximately preserves the quadratic form of G, i.e., for all vectors x, x~T L_G x ≈ x~T L_H x, where L_G and L_H denote the respective graph Laplacians. Spectral sparsifiers generalize cut sparsifiers, and have found many applications in designing graph algorithms. In recent years, there has been interest in computing spectral sparsifiers in semi-streaming and dynamic settings. Natural algorithms in these settings often involve repeated sparsification of a graph, and in turn accumulation of errors across these steps. We present a framework for analyzing algorithms that perform repeated sparsifications that only incur error corresponding to a single sparsification step, leading to better results for many of these reseparsification based algorithms. As an application, we show how to maintain a spectral sparsifier in the semi-streaming setting: We present a simple algorithm that, for a graph G on n vertices and m edges, computes a spectral sparsifier of G with O(n log n) edges in a single pass over G, using only O(n log n) space, and O(m log~2 n) total time. This improves on previous best semi-streaming algorithms for both spectral and cut sparsifiers by a factor of log n in both space and runtime. The algorithm also extends to semi-streaming row sampling for general PSD matrices. As another application, we use this framework to combine a spectral sparsification algorithm by Koutis with improved spanner constructions to give a parallel algorithm for constructing O(n log~2 n log log n) sized spectral sparsifiers in O(m log~2 n log log n) time. This is the best combinatorial graph sparsification algorithm to date, and the size of the sparsifiers produced is only a factor log n log log n more than ones produced by numerical routines.

关键词： logs logarithm (log) algorithms Line graph Frameworks Graph algorithms Quadratic form parallel algorithms

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The design of bit-parallel systolic filter algorithms 84

The design of bit-parallel systolic filter algorithms

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Proceedings of the acm 12th annual computer science conference on SIGCSE symposium

作者： Paul L. Mills

ISBN: (纸本)9780897911276

In this paper we present a methodology for the design of systolic arrays for numeric and non-numeric (symbolic) systolic functions. This methodology is then applied to the Finite Impulse Response (F.I.R) Filter function. A particular design approach is followed and we present the complete design procedure and specification for a two-stage, two-bit input data and two-bit reference coefficient bit parallel filter.

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