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检索条件"任意字段=Annual ACM Symposium on Parallel Algorithms and Architectures"

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Processor-efficient parallel solution of linear systems. II. The positive characteristic and singular cases

Processor-efficient parallel solution of linear systems. II....

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annual IEEE symposium on Foundations of Computer Science

作者： E. Kaltofen V. Pan Department of Computer Science Rensselaer Polytechnic Institute Troy NY USA Department of Mathematics and Computer Science Lehman College of the City University of New York Bronx NY USA

For pt.I see Proc. 3rd Ann. acm Symp. parallel Algms. Architecture, p. 180-91 (1991). The authors show that over any field, the solution set to a system of n linear equations in n unknowns can be computed in parallel with randomization simultaneously in poly-logarithmic time in n and with only as many processors as are utilized to multiply two n * n matrices. A time unit represents an arithmetic operation in the field. For singular systems the parallel timings are asymptotically as fast as those for non-singular systems, due to the avoidance of binary search in the matrix rank problem, except when the field has small positive characteristic; in that case, binary search is avoided at a somewhat higher processor count measure.< >

关键词： Linear systems parallel algorithms Computer science Concurrent computing Algorithm design and analysis Economic indicators Mathematics Educational institutions Equations Arithmetic

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Multiplier architectures for FPGA double precision functions (abstract only) 10

Multiplier architectures for FPGA double precision functions...

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Proceedings of the 18th annual acm/SIGDA international symposium on Field programmable gate arrays

作者： Y. Hamid Martin Langhammer Altera Corporation Penang Malaysia Altera Corporation High Wycombe United Kingdom

ISBN: (纸本)9781605589114

FPGA devices are now more capable at supporting floating point applications, but double precision IEEE754 systems are still very challenging to implement, with large amounts of logic, routing, and DSP resources needed. Double precision multiplier operators, requiring 54x54 multiplier cores, are now directly supported in the fabric, however, multiplier based algorithms for algebraic and elementary functions typically require larger multiplier functions, typically in excess of 60x60 bits precision. This paper will use the example of a double precision exp (ex) to explore tradeoffs with multiplier architectures mapped to current FPGAs devices. Different types of the larger multiplier architectures, including direct implementations and Karatsuba-Ofman algorithms will be compared, including their effect on the resource requirements and system performance of the exp function. Smaller multiplier architectures, which introduce a small maximum functional error, will also be *** large multiplier architectures can provide the same accuracy with increased system performance, with up to 33% less multiplier resources. Smaller multiplier will reduce the multiplier resources by up to 50%, albeit with a small maximum error, in the range of 5 ulp.

关键词： fpga floating point

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On the network complexity of selection

On the network complexity of selection

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annual IEEE symposium on Foundations of Computer Science

作者： C.G. Plaxton Department of Computer Science University of Stanford Stanford CA USA

The sequential complexity of determining the kth largest out of a given set of n keys is known to be linear. Thus, given a p-processor parallel machine, it is asked whether or not an O(n/p) selection algorithm can be devised for that machine. An Omega ((n/p) log log p+log p) lower bound is obtained for selection on any network that satisfies a particular low expansion property. The class of networks satisfying this property includes all of the common network families, such as the tree, multidimensional mesh, hypercube, butterfly, and shuffle-exchange. When n/p is sufficiently large (e.g. greater than log/sup 2/p on the butterfly, hypercube, and shuffle-exchange), this result is matched by the upper bound given previously by the author (Proc. 1st Ann. acm Symp. on parallel algorithms and Architecture p.64-73, 1989).< >

关键词： Hypercubes Upper bound Computer science parallel machines Multiprocessor interconnection networks Communication channels

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Increasing the instruction fetch rate via block-structured instruction set architectures 29

Increasing the instruction fetch rate via block-structured i...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： E. Hao Po-Yung Chang M. Evers Y.N. Patt Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818676413

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rare. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the instruction fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.

关键词： Instruction sets Computer architecture parallel processing Sun Laboratories Microarchitecture Dynamic scheduling Pipelines Program processors Hardware

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On the parallel time complexity of undirected connectivity and minimum spanning trees 99

On the parallel time complexity of undirected connectivity a...

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Proceedings of the tenth annual acm-SIAM symposium on Discrete algorithms

作者： Ka Wong Chong Yijie Han Tak Wah Lam Max-Planck-Institut für Informatik 66123 Saarbrücken Germany Electronic Data Systems Inc. 750 Tower Drive Mail Stop 7121 CPS Troy MI Department of Computer Science The University of Hong Kong Hong Kong

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Lopsidependency in the Moser-Tardos framework: Beyond the Lopsided Lovasz Local Lemma 15

Lopsidependency in the Moser-Tardos framework: Beyond the Lo...

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annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： David G. Harris Department of Applied Mathematics University of Maryland

ISBN: (纸本)9781510813311

The Lopsided Lovasz Local Lemma (LLLL) is a powerful probabilistic principle which has been used in a variety of combinatorial constructions. While this principle began as a general statement about probability spaces, it has recently been transformed into a variety of polynomial-time algorithms. The resampling algorithm of Moser & Tardos is the most well-known example of this. A variety of criteria have been shown for the LLLL; the strongest possible criterion was shown by Shearer, and other criteria which are easier to use computationally have been shown by Bissacot et al, Pegden, and Kolipaka & Szegedy. We show a new criterion for the Moser-Tardos algorithm to converge. This criterion is stronger than the LLLL criterion, and in fact can yield better results even than the full Shearer criterion. This is possible because it does not apply in the same generality as the original LLLL; yet, it is strong enough to cover many applications of the LLLL in combinatorics. We show a variety of new bounds and algorithms. A noteworthy application is for k-SAT, with bounded occurences of variables. As shown in Gebauer, Szabo, and Tardos, a k-SAT instance in which every variable appears L ≤ 2~(k+1)/(e(k+1)) times, is satisfiable. Although this bound is asymptotically tight (in k), we improve it to L ≤ (2~(k+1)(1-1/k)~k)/(k-1) - 2/k which can be significantly stronger when k is small. We introduce a new parallel algorithm for the LLLL. While Moser & Tardos described a simple parallel algorithm for the Lovasz Local Lemma, and described a simple sequential algorithm for a form of the Lopsided Lemma, they were not able to combine the two. Our new algorithm applies in nearly all settings in which the sequential algorithm works - this includes settings covered by our new stronger LLLL criterion.

关键词： parallel algorithms Lemma winning and haulage machine sequential algorithm Combinatorics algorithms Probability

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Performance evaluation of packet processing architectures using multiclass queuing networks

Performance evaluation of packet processing architectures us...

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annual symposium on Simulation

作者： S. Sonntag M. Gries C. Sauer Wireline Access Communication Infineon Technologies Munich Germany

Modern real-time systems consist of complex parallel and heterogeneous architectures. Early design decisions, such as the partitioning of functionality onto architecture building blocks and the choice of algorithms, have a large impact on the quality of the resulting platform. In order to support the designer during this concept phase, we have developed our performance evaluation framework SystemQ. In this paper, we demonstrate why multiclass queuing networks as used by SystemQ are a natural abstraction for evaluating network processing platforms. In particular, we reveal the impact of scheduling policies on the quality-of-service, such as the residence time of network traffic in the system. For the same stimuli, the packet latency can vary by more than one order of magnitude if only one queuing discipline in the system is modified.

关键词： Hardware Telecommunication traffic Traffic control Costs Phase estimation Queueing analysis Computer architecture Communications technology Real time systems Algorithm design and analysis

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Massively-parallel Similarity Join, Edge-Isoperimetry, and Distance Correlations on the Hypercube 17

Massively-Parallel Similarity Join, Edge-Isoperimetry, and D...

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annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Paul Beame Cyrus Rashtchian Computer Science & Engineering University of Washington

ISBN: (纸本)9781510836358

We study distributed protocols for finding all pairs of similar vectors in a large dataset. Our results pertain to a variety of discrete metrics, and we give concrete instantiations for Hamming distance. In particular, we give improved upper bounds on the overhead required for similarity defined by Hamming distance r > 1 and prove a lower bound showing qualitative optimality of the overhead required for similarity over any Hamming distance r. Our main conceptual contribution is a connection between similarity search algorithms and certain graph-theoretic quantities. For our upper bounds, we exhibit a general method for designing one-round protocols using edge-isoperimetric shapes in similarity graphs. For our lower bounds, we define a new combinatorial optimization problem, which can be stated in purely graph-theoretic terms yet also captures the core of the analysis in previous theoretical work on distributed similarity joins. As one of our main technical results, we prove new bounds on distance correlations in subsets of the Hamming cube.

关键词： Hamming distance Hypercube Upper bound distributed protocol Core analysis Lower bound

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An empirical study to compare two parallel programming models 06

An empirical study to compare two parallel programming model...

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Proceedings of the eighteenth annual acm symposium on parallelism in algorithms and architectures

作者： Lorin Hochstein Victor R. Basili University of Maryland College Park MD

ISBN: (纸本)9781595934529

While there are strong beliefs within the community about whether one particular parallel programming model is easier to use than another, there has been little research to analyze these claims empirically. Currently, the most popular paradigm is message-passing, as implemented by the MPI library [1]. However, MPI is considered to be difficult for developing programs, because it forces the programmer to work at a very low level of abstraction. One alternative parallel programming model is the PRAM model, which supports fine-grained parallelism and has a substantial history of algorithmic theory [2]. It is not possible to program current parallel machines using the PRAM model because modern architectures are not designed to support such a model efficiently. However, current trends towards multicore chips suggest that large-scale, fine-grained uniform-memory access parallel machines may soon be feasible. XMT-C is an extension of the C language that supports parallel directives to provide a PRAM-like model to the programmer. A prototype compiler exists that generates code which runs on a simulator for an XMT architecture [3].To better understand how much benefit a PRAM-like model could provide over a message-passing model, we conducted a feasibility study in an academic setting to compare the effort required to solve a particular problem. The questions under study were: can we measure the effort in developing a program using these two programming models and can we differentiate the amount of effort for each model?.The subjects participating in the study were divided up into two groups. One group solved a problem using the MPI library in either C,C++, or Fortran, and the other group solved the problem using XMT-C. The task was to write a function to multiply a sparse matrix with a dense vector. To obtain subjects, we leveraged existing graduate-level parallel programming courses at two different universities: University of California, Santa Barbara (UCSB), and Universit

关键词： HPC message-passing PRAM XMT empirical study productivity effort parallel programming MPI

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A Compiler-Runtime Application Binary Interface for Pipe-While Loops 15

A Compiler-Runtime Application Binary Interface for Pipe-Whi...

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Proceedings of the 27th acm symposium on parallelism in algorithms and architectures

作者： Jim Sukha Intel Corporation Hudson MA USA

ISBN: (纸本)9781450335881

Pipe-while loops have been proposed as a language construct for expressing pipeline parallelism in task-parallel languages. However, this loop construct has only been prototyped in research systems that lack compiler support. We demonstrate how to extend Intel® Cilk™ Plus, a production-quality task-parallel language, to implement pipe-while loops. We propose an extension to the compiler-runtime application binary interface (ABI) of Cilk Plus to support pipe-while loops. This extension maintains compatibility with existing language constructs and existing Cilk Plus binaries. We validate this ABI by prototyping the required runtime modifications and simulating the required front-end compiler transformations using preprocessor macros and C++ lambda functions.

关键词： pipeline loops pipe-while loops parallel programming cilk plus task parallelism

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