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Eccentricities via parallel Set Cover (Brief Announcement) 19

Eccentricities via Parallel Set Cover (Brief Announcement)

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The 31st acm symposium on parallelism in algorithms and architectures

作者： Tal Wagner MIT Cambridge MA USA

ISBN: (纸本)9781450361842

The eccentricity of a node in a graph G(V,E) is its maximal shortest-path distance to any other node. Shun (KDD 2015) suggested a simple heuristic for computing all eccentricities in an input graph, based on two-phase parallel BFS from a small sample of nodes. It was shown to outperform state-of-the-art algorithms by up to orders of magnitude. This empirical success stands in apparent contrast to recent theoretical hardness results on approximating all eccentricities (Backurs et al., STOC 2018). This note aims to formally explain the performance of this heuristic, by drawing a connection to the streaming Set Cover algorithm of Demaine et al. (DISC 2014). We use it to suggest a variant with similar work and depth bounds, which is guaranteed to compute almost all eccentricities exactly, if the graph satisfies a condition we call small eccentric periphery. The condition can be ascertained for all real-world graph used in Shun (KDD 2015) and in our experiments. Experimental results demonstrate the validity of the analysis and the empirical advantage of our proposed variant.

关键词： set cover eccentricity k-BFS

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Two-level hierarchical register file organization for VLIW processors

Two-level hierarchical register file organization for VLIW p...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： J. Zalamea J. Llosa E. Ayguade M. Valero Department d'Arquitectura de Computadors Universitat Poliltècnica de Catalunya Spain

High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. If more registers than those available in the architecture are required, some actions (such as spill code insertion) have to be applied to reduce this pressure, at the expense of some performance degradation. This degradation could be avoided if a high-capacity register file were included without causing a negative impact on the cycle time of the processor. The authors propose a two-level hierarchical register file organization for VLIW architectures that combines high capacity and low access time. For the configuration proposed in the paper, the new organization achieves a speed-up of 10-14% over a monolithic organization with 64 registers; it is obtained with a 43% (40%) reduction in area (peak power dissipation). Compared to a monolithic file with 32 registers, the speed-up is as much as 38% with just a 14% (4%) increase in area (peak power dissipation).

关键词： Registers VLIW Processor scheduling parallel processing Pipeline processing Microprocessors Degradation Power dissipation Dynamic scheduling Computer aided instruction

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parallel batch-dynamic graphs: algorithms and lower bounds 20

Parallel batch-dynamic graphs: algorithms and lower bounds

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Proceedings of the Thirty-First annual acm-SIAM symposium on Discrete algorithms

作者： Laxman Dhulipala David Durfee Janardhan Kulkarni Richard Peng Saurabh Sawlani Xiaorui Sun Carnegie Mellon University LinkedIn Microsoft Research Georgia Tech University of Illinois at Chicago

In this paper we study the problem of dynamically maintaining graph properties under batches of edge insertions and deletions in the massively parallel model of computation. In this setting, the graph is stored on a number of machines, each having space strongly sublinear with respect to the number of vertices, that is, nε for some constant 0 < ε < 1. Our goal is to handle batches of updates and queries where the data for each batch fits onto one machine in constant rounds of parallel computation, as well as to reduce the total communication between the machines. This objective corresponds to the gradual buildup of databases over time, while the goal of obtaining constant rounds of communication for problems in the static setting has been elusive for problems as simple as undirected graph *** give an algorithm for dynamic graph connectivity in this setting with constant communication rounds and communication cost almost linear in terms of the batch size. Our techniques combine a new graph contraction technique, an independent random sample extractor from correlated samples, as well as distributed data structures supporting parallel updates and queries in *** also illustrate the power of dynamic algorithms in the MPC model by showing that the batched version of the adaptive connectivity problem is P-complete in the centralized setting, but sub-linear sized batches can be handled in a constant number of rounds. Due to the wide applicability of our approaches, we believe it represents a practically-motivated workaround to the current difficulties in designing more efficient massively parallel static graph algorithms.

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Heuristics for register-constrained software pipelining 29

Heuristics for register-constrained software pipelining

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： J. Llosa M. Valero E. Ayguade Departament dE28099Arquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain

ISBN: (纸本)9780818676413

Software Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal schedules under resource constraints, and more recently to produce throughput-optimal schedules with minimum register requirements. Unfortunately even a throughput-optimal schedule with minimum register requirements is useless if it requires more registers than those available in the target machine. This paper evaluates several techniques for producing register-constrained modulo schedules: increasing the initiation interval (II) and adding spill code. We show that, in general, increasing the II performs poorly and might not converge for some loops. The paper also presents an iterative spilling mechanism that can be applied to any software pipelining technique and proposes several heuristics in order to speed-up the scheduling process.

关键词： Pipeline processing Registers Concurrent computing Processor scheduling parallel processing Software algorithms Scheduling algorithm Contracts Production

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Instruction scheduling for the Motorola 88110 26

Instruction scheduling for the Motorola 88110

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Mark Smotherman Shuchi Chawla Stan Cox Brian Malloy Department of Electrical Engineering Tel-Aviv University Tel-Aviv Israel Department of Computer Science Clemson University Clemson SC

ISBN: (纸本)9780818652806

Static instruction scheduling is an important optimization to exploit instruction level parallelism. If the scheduler has to consider resource constraints to prevent structural hazards, usually the processor timing is simulated by overlaying binary matrices representing the resource usage of instructions. This technique is rather time consuming. It is shown that the timing can be simulated by a deterministic finite automaton and the matrix operations for a simulation step are replaced by two table lookups. A prototype implementation shows that about an eighteenfold speedup of the simulation can be expected. This performance gain can be used either to speed up existing scheduling algorithms or to use more complex algorithms to improve scheduling results.< >

关键词： Automata Hazards Processor scheduling Vents Prototypes parallel processing Runtime Delay Time measurement Timing

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Links-1 - a parallel pipelined multimicrocomputer system for image creation 83

Links-1 - a parallel pipelined multimicrocomputer system for...

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Proceedings of the 10th annual international symposium on Computer architecture

作者： Hitoshi Nishimura Hiroshi Ohno Toru Kawata Isao Shirakawa Koichi Omura

ISBN: (纸本)9780897911016

A multimicrocomputer system is described, stressing mainly software and hardware architectures, which has been constructed mainly for image creation. This system is distinctive mainly in that (i) 64 unit computers are interconnected with a root computer, each of equal performance, such that a number of unit computers constitute a pipelined computer and such pipelined computers work in parallel, all controlled by the root computer, and (ii) an intercomputer memory swapping unit is introduced, which is to be linked with a pair of unit computers to transfer a great amount of data at a time from one to the other through the use of a bus exchange switch.

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Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore

Scalable, Programmable and Dense: The HammerBlade Open-Sourc...

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annual International symposium on Computer Architecture, ISCA

作者： Dai Cheol Jung Max Ruttenberg Paul Gao Scott Davidson Daniel Petrisko Kangli Li Aditya K Kamath Lin Cheng Shaolin Xie Peitian Pan Zhongyuan Zhao Zichao Yue Bandhav Veluri Sripathi Muralitharan Adrian Sampson Andrew Lumsdaine Zhiru Zhang Christopher Batten Mark Oskin Dustin Richmond Michael Bedford Taylor University of Washington Cornell University PNNL University of California Santa Cruz

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However, as we approach 100 K cores in one chip, conventional manycore architectures struggle to navigate three key axes: scalability, programmability, and density. Many manycores sacrifice programmability for density; or scalability for programmability. In this paper, we explore HammerBlade, which simultaneously achieves scalability, programmability and density. HammerBlade is a fully open-source RISC-V manycore architecture, which has been silicon-validated with a 2048-core ASIC implementation using a 14/16nm process. We evaluate the system using a suite of parallel benchmarks that captures a broad spectrum of computation and communication patterns.

关键词： Scalability Instruction sets Source coding Computer architecture Voltage parallel processing Silicon

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Tight bounds for parallel paging and green paging 21

Tight bounds for parallel paging and green paging

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Kunal Agrawal Michael A. Bender Rathish Das William Kuszmaul Enoch Peserico Michele Scquizzato Washington University in St. Louis Stony Brook University MIT Università degli Studi di Padova Italy

ISBN: (纸本)9781611976465

In the parallel paging problem, there are p processors that share a cache of size k. The goal is to partition the cache among the processors over time in order to minimize their average completion time. For this long-standing open problem, we give tight upper and lower bounds of Θ(log p) on the competitive ratio with O(1) resource augmentation.A key idea in both our algorithms and lower bounds is to relate the problem of parallel paging to the seemingly unrelated problem of green paging. In green paging, there is an energy-optimized processor that can temporarily turn off one or more of its cache banks (thereby reducing power consumption), so that the cache size varies between a maximum size k and a minimum size k/p. The goal is to minimize the total energy consumed by the computation, which is proportional to the integral of the cache size over *** show that any efficient solution to green paging can be converted into an efficient solution to parallel paging, and that any lower bound for green paging can be converted into a lower bound for parallel paging, in both cases in a black-box fashion. We then show that, with O(1) resource augmentation, the optimal competitive ratio for deterministic online green paging is Θ(log p), which, in turn, implies the same bounds for deterministic online parallel paging.

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Efficient sequential and parallel algorithms for computing recovery points in trees and paths 91

Efficient sequential and parallel algorithms for computing r...

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Proceedings of the second annual acm-SIAM symposium on Discrete algorithms

作者： Marek Chrobak David Eppstein Giuseppe F. Italiano Moti Yung Department of Computer Science University of California Riverside CA Xerox PARC Palo Alto CA and University of California Irvine CA and Columbia University New York NY Department of Computer Science Columbia University New York NY and Dipartimento di Informatica e Sistemistica Università di Roma 'La Sapienza' Roma Italy IBM Research Division T.J. Watson Research Center Yorktown Heights NY

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Tight analysis of parallel randomized greedy MIS 18

Tight analysis of parallel randomized greedy MIS

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Proceedings of the Twenty-Ninth annual acm-SIAM symposium on Discrete algorithms

作者： Manuela Fischer Andreas Noever ETH Zurich

ISBN: (纸本)9781611975031

We provide a tight analysis which settles the round complexity of the well-studied parallel randomized greedy MIS algorithm, thus answering the main open question of Blelloch, Fineman, and Shun [SPAA'12].The parallel/distributed randomized greedy Maximal Independent Set (MIS) algorithm works as follows. An order of the vertices is chosen uniformly at random. Then, in each round, all vertices that appear before their neighbors in the order are added to the independent set and removed from the graph along with their neighbors. The main question of interest is the number of rounds it takes until the graph is empty. This algorithm has been studied since 1987, initiated by Coppersmith, Raghavan, and Tompa [FOCS'87], and the previously best known bounds were O(log n) rounds in expectation for Erdős-Rényi random graphs by Calkin and Frieze [Random Struc. & Alg. '90] and O(log2 n) rounds with high probability for general graphs by Blelloch, Fineman, and Shun [SPAA'12].We prove a high probability upper bound of O(log n) on the round complexity of this algorithm in general graphs, and that this bound is tight. This also shows that parallel randomized greedy MIS is as fast as the celebrated algorithm of Luby [STOC'85, JALG'86].

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