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Tight bounds for parallel paging and green paging 21

Tight bounds for parallel paging and green paging

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Kunal Agrawal Michael A. Bender Rathish Das William Kuszmaul Enoch Peserico Michele Scquizzato Washington University in St. Louis Stony Brook University MIT Università degli Studi di Padova Italy

ISBN: (纸本)9781611976465

In the parallel paging problem, there are p processors that share a cache of size k. The goal is to partition the cache among the processors over time in order to minimize their average completion time. For this long-standing open problem, we give tight upper and lower bounds of Θ(log p) on the competitive ratio with O(1) resource augmentation.A key idea in both our algorithms and lower bounds is to relate the problem of parallel paging to the seemingly unrelated problem of green paging. In green paging, there is an energy-optimized processor that can temporarily turn off one or more of its cache banks (thereby reducing power consumption), so that the cache size varies between a maximum size k and a minimum size k/p. The goal is to minimize the total energy consumed by the computation, which is proportional to the integral of the cache size over *** show that any efficient solution to green paging can be converted into an efficient solution to parallel paging, and that any lower bound for green paging can be converted into a lower bound for parallel paging, in both cases in a black-box fashion. We then show that, with O(1) resource augmentation, the optimal competitive ratio for deterministic online green paging is Θ(log p), which, in turn, implies the same bounds for deterministic online parallel paging.

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Efficient sequential and parallel algorithms for computing recovery points in trees and paths 91

Efficient sequential and parallel algorithms for computing r...

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Proceedings of the second annual acm-SIAM symposium on Discrete algorithms

作者： Marek Chrobak David Eppstein Giuseppe F. Italiano Moti Yung Department of Computer Science University of California Riverside CA Xerox PARC Palo Alto CA and University of California Irvine CA and Columbia University New York NY Department of Computer Science Columbia University New York NY and Dipartimento di Informatica e Sistemistica Università di Roma 'La Sapienza' Roma Italy IBM Research Division T.J. Watson Research Center Yorktown Heights NY

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Tight analysis of parallel randomized greedy MIS 18

Tight analysis of parallel randomized greedy MIS

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Proceedings of the Twenty-Ninth annual acm-SIAM symposium on Discrete algorithms

作者： Manuela Fischer Andreas Noever ETH Zurich

ISBN: (纸本)9781611975031

We provide a tight analysis which settles the round complexity of the well-studied parallel randomized greedy MIS algorithm, thus answering the main open question of Blelloch, Fineman, and Shun [SPAA'12].The parallel/distributed randomized greedy Maximal Independent Set (MIS) algorithm works as follows. An order of the vertices is chosen uniformly at random. Then, in each round, all vertices that appear before their neighbors in the order are added to the independent set and removed from the graph along with their neighbors. The main question of interest is the number of rounds it takes until the graph is empty. This algorithm has been studied since 1987, initiated by Coppersmith, Raghavan, and Tompa [FOCS'87], and the previously best known bounds were O(log n) rounds in expectation for Erdős-Rényi random graphs by Calkin and Frieze [Random Struc. & Alg. '90] and O(log2 n) rounds with high probability for general graphs by Blelloch, Fineman, and Shun [SPAA'12].We prove a high probability upper bound of O(log n) on the round complexity of this algorithm in general graphs, and that this bound is tight. This also shows that parallel randomized greedy MIS is as fast as the celebrated algorithm of Luby [STOC'85, JALG'86].

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Graphicionado: A high-performance and energy-efficient accelerator for graph analytics 49

Graphicionado: A high-performance and energy-efficient accel...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Tae Jun Ham Lisa Wu Narayanan Sundaram Nadathur Satish Margaret Martonosi Princeton University University of California Berkeley Parallel Computing Lab Intel Corporation

ISBN: (纸本)9781509035090

Graphs are one of the key data structures for many real-world computing applications and the importance of graph analytics is ever-growing. While existing software graph processing frameworks improve programmability of graph analytics, underlying general purpose processors still limit the performance and energy efficiency of graph analytics. We architect a domain-specific accelerator, Graphicionado, for high-performance, energy-efficient processing of graph analytics workloads. For efficient graph analytics processing, Graphicionado exploits not only data structure-centric datapath specialization, but also memory subsystem specialization, all the while taking advantage of the parallelism inherent in this domain. Graphicionado augments the vertex programming paradigm, allowing different graph analytics applications to be mapped to the same accelerator framework, while maintaining flexibility through a small set of reconfigurable blocks. This paper describes Graphicionado pipeline design choices in detail and gives insights on how Graphicionado combats application execution inefficiencies on general-purpose CPUs. Our results show that Graphicionado achieves a 1.76-6.54x speedup while consuming 50-100x less energy compared to a state-of-the-art software graph analytics processing framework executing 32 threads on a 16-core Haswell Xeon processor.

关键词： Software Programming Software algorithms Machine learning algorithms System-on-chip Pipelines Memory management

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Efficient algorithms for Constructing Very Sparse Spanners and Emulators 17

Efficient Algorithms for Constructing Very Sparse Spanners a...

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annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Michael Elkin Ofer Neiman Department of Computer Science Ben-Gurion University of the Negev

ISBN: (纸本)9781510836358

Miller et al. [43] devised a distributed algorithm in the CONGEST model, that given a parameter k = 1, 2,..., constructs an O(k)-spanner of an input unweighted n-vertex graph with O(n~(1+1/k)) expected edges in O(k) rounds of communication. In this paper we improve the result of [43], by showing a k-round distributed algorithm in the same model, that constructs a (2k - 1)-spanner with O(n~(1+1/k)/ε) edges, with probability 1 - ε, for any ε > 0. Moreover, when k = ω(log n), our algorithm produces (still in k rounds) ultra-sparse spanners, i.e., spanners of size n(1 + o(1)), with probability 1 - o(1). To our knowledge, this is the first distributed algorithm in the CONGEST or in the PRAM models that constructs spanners or skeletons (i.e., connected spanning subgraphs) that sparse. Our algorithm can also be implemented in linear time in the standard centralized model, and for large k, it provides spanners that are sparser than any other spanner given by a known (near-)linear time algorithm. We also devise improved bounds (and algorithms realizing these bounds) for (1 + ε, β)-spanners and emulators. In particular, we show that for any un-weighted n-vertex graph and any ε > 0, there exists a (1 + ε, (log log n/ε)~(log log n))-emulator with O(n) edges. All previous constructions of (1 + ε, β)-spanners and emulators employ a superlinear number of edges, for all choices of parameters. Finally, we provide some applications of our results to approximate shortest paths' computation in un-weighted graphs.

关键词： spanners Emulators distributed algorithms algorithms efficient algorithm parallel random access machine model Skeletons

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Composable Lightweight Processors 40

Composable Lightweight Processors

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Changkyu Kim Simha Sethumadhavan M.S. Govindan Nitya Ranganathan Divya Gulati Doug Burger Stephen W. Keckler Microprocessor Technology Laboratories Intel Corporation USA Department of Computer Sciences University of Texas Austin USA

ISBN: (纸本)9780769530475

Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processors. However, the number of processors and the granularity of each processor are fixed at design time. This paper evaluates a flexible architectural approach, called composable lightweight processors (or CLPs), that allows simple, low-power cores to be aggregated together dynamically, forming larger, more powerful single-threaded processors without changing the application binary. We evaluate one such design with 32 cores called TFlex, which can be configured as 32 dual-issue processors, or as a single 64-wide issue processor, or as any point in between. Use of an explicit data graph execution (EDGE) ISA enables the system to be fully composable, with no monolithic structures spanning the cores. Simulation results show that CLPs achieve an average performance boost of 42%, an average area-efficiency of 3.4x, and an average power-efficiency of 2x over a fixed architecture on a spectrum of single-threaded applications. Results also show that CLPs outperform a spectrum of fixed CMP architectures on a set of multitasking workloads.

关键词： Yarn Energy efficiency Microarchitecture parallel processing Computer architecture Runtime Software performance Microprocessors Instruction sets Application software

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MASA: a multithreaded processor architecture for parallel symbolic computing 88

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Proceedings of the 15th annual International symposium on Computer architecture

作者： R. H. Halstead, Jr. T. Fujita MIT Cambridge MA NEC Tokyo Japan

ISBN: (纸本)9780818608612

MASA is a “first cut” at a processor architecture intended as a building block for a multiprocessor that can execute parallel Lisp programs efficiently. MASA features a tagged architecture, multiple contexts, fast trap handling, and a synchronization bit in every memory word. MASA's principal novelty is its use of multiple contexts both to support multithreaded execution—interleaved execution from separate instruction streams—and to speed up procedure calls and trap handling in the same manner as register windows. A project is under way to evaluate MASA-like architectures for executing programs written in Multilisp.

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parallel programmable finite field GF (2/sup m/) multipliers

Parallel programmable finite field GF (2/sup m/) multipliers

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IEEE Computer Society annual symposium on VLSI

作者： N. Iliev J.E. Stine N. Jachimiec VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Block (cyclic) channel coding standards for third generation cellular networks require the implementation of high-performance burst-error detection and correction algorithms. Galois field (GF) arithmetic is commonly used in this architecture for encoding and decoding error codes, however, many architectures still do not support dedicated functional units. This paper presents the design of a generic parallel finite-field GF (2/sup m/) multiplier targeted at DSP and embedded processors. As opposed to previous research, this design has the ability to utilize different primitive polynomials as an input, thereby, being able to be programmable. Moreover, a design is presented that is a combined binary and finite-field GF (2/sup m/) multiplier. Area, delay, and power dissipation results are presented from several ASIC libraries.

关键词： Galois fields Channel coding Land mobile radio cellular systems Arithmetic Decoding Digital signal processing Polynomials Delay Power dissipation Application specific integrated circuits

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parallel processor scheduling with delay constraints 01

Parallel processor scheduling with delay constraints

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Proceedings of the twelfth annual acm-SIAM symposium on Discrete algorithms

作者： Daniel W. Engels Jon Feldman David R. Karger Matthias Ruhl MIT Laboratory for Computer Science Cambridge MA

ISBN: (纸本)9780898714906

We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose a partial order on the jobs, and both communication and precedence delays impose relative timing constraints on dependent jobs. The combination of these two types of timing constraints naturally models the instruction scheduling problem that occurs during software compilation for state-of-the-art VLIW (Very Long Instruction Word) processors and multiprocessor parallel *** present the first known polynomial-time algorithm for the case where the precedence constraint graph is a forest of in-trees (or a forest of out-trees), the number of machines m is fixed, and the delays (which are a function of both the job pair and the machines on which they run) are bounded by a constant *** algorithm relies on a new structural theorem for scheduling jobs with arbitrary precedence constraints. Given an instance with many independent dags, the theorem shows how to convert, in linear time, a schedule S for only the largest dags into a complete schedule that is either optimal or has the same makespan as S.

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Fast and guaranteed C compilation onto the PACT-XPP/spl trade/ reconfigurable computing platform

Fast and guaranteed C compilation onto the PACT-XPP/spl trad...

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annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： J.M.P. Cardoso M. Weinhardt PACT Informationstechnologie AG Munich Germany

We introduce the XPP-VC high-level compiler, which maps C programs to the coarse-grained XPP architecture. XPP-VC's main feature is the integration of pipeline vectorization and temporal partitioning techniques. The former provides high-throughput inner loop computations and the later allows the compilation of large programs or the use of fewer XPP processing elements. Although the preliminary results are very encouraging, improvements on the generation of configurations are still required. The evaluation we have conducted shows that only a few seconds are required to generate, from algorithms in C, the binaries to program the XPP. To our knowledge this compilation performance is unmatched by any other compiler targeting reconfigurable architectures. Moreover the compiler still achieves high-performance implementations. Since the XPP is delivered as an IP core or device to be coupled to a host processor, a future version of XPP-VC will consider co-compilation, i.e., compilation to hybrid microprocessor/XPP architectures.

关键词： Computer architecture Field programmable gate arrays Concurrent computing High performance computing Roads parallel processing Adaptive arrays Array signal processing LAN interconnection Frequency synchronization

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