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Fast parallel processing array algorithms for some graph problems(Preliminary Version) 79

Fast parallel processing array algorithms for some graph pro...

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Proceedings of the eleventh annual acm symposium on Theory of computing

作者： S. Rao Kosaraju

ISBN: (纸本)9781450374385

The parallel processing array consists of an n×n array of processors to which a cn2 node directed graph can be input by placing c nodes at every point of the array. It is shown that every one of the following properties of the graph can be computed in order of n steps:(1) to test whether the graph is strongly connected,(2) to mark a node in every strongly connected component,(3) to mark a strong connected component that contains a given node,(4) to mark a simple directed path between a given pair of nodes, and(5) to compute the interconnectivity of the c nodes within every *** a consequence, several open problems can be solved. For example, any language recognized by a 2-dimensional finite state automaton with 1 pebble can be recognized in order of n steps by a parallel processing array. (It was not even known whether the languages recognized by 2-dimensional finite state automata without pebbles can be recognized in order of n steps by a parallel processing array). Note that a 1 pebble automaton can run for order of n4 steps before accepting an input.

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Submodular Function Maximization in parallel via the Multilinear Relaxation 19

Submodular Function Maximization in Parallel via the Multili...

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annual acm-SIAM symposium on Discrete algorithms

作者： Chandra Chekuri Kent Quanrud University of Illinois

Balkanski and Singer recently initiated the study of adaptivity (or parallelism) for constrained submodular function maximization, and studied the setting of a cardinality constraint. Subsequent improvements for this problem by Balkanski, Rubinstein, and Singer and Ene and Nguyen resulted in a near-optimal (1 -1/e - ε)-approximation in O(log n/ε~2) rounds of adaptivity. Partly motivated by the goal of extending these results to more general constraints, we describe parallel algorithms for approximately maximizing the multilinear relaxation of a monotone submodular function subject to packing constraints. Formally our problem is to maximize F(x) over x ∈ [0, 1]~n subject to Ax ≤ 1 where F is multilinear relaxation of a monotone sub-modular function. Our algorithm achieves a near-optimal (1 - 1/e - ε)-approximation in O(log~2 m log n/ε~4) rounds where n is the cardinality of the ground set and m is the number of packing constraints. For many constraints of interest, the resulting fractional solution can be rounded via known randomized rounding schemes that are oblivious to the specific submcodular function. We thus derive randomized algorithms with poly-logarithmic adaptivity for a number of constraints including partition and laminar matroids, matchings, knapsack constraints, and their intersections. Our algorithm takes a continuous view point and combines several ideas ranging from the continuous greedy algorithm of [38, 13], its adaptation to the MWU framework for packing constraints, and parallel algorithms for packing LPs. For the basic setting of cardinality constraints, this viewpoint gives rise to an alternative, simple to understand algorithm that matches recent results. Our algorithm to solve the multilinear relaxation is deterministic if it is given access to a value oracle for the multilinear extension and its gradient;this is possible in some interesting cases such as the coverage function of an explicitly given set system.

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parallel algorithms and architectures for rule-based systems 86

Parallel algorithms and architectures for rule-based systems

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Proceedings of the 13th annual international symposium on Computer architecture

作者： A. Gupta C. Forgy A. Newell R. Wedig Carnegie-Mellon UniversityPittsburgh Pennsylvania

ISBN: (纸本)9780818607196

Rule-based systems, on the surface, appear to be capable of exploiting large amounts of parallelism—it is possible to match each rule to the data memory in parallel. In practice, however, we show that the speed-up from parallelism is quite limited, less than 10-fold. The reasons for the small speed-up are: (1) the small number of rules relevant to each change to data memory; (2) the large variation in the processing required by the relevant rules; and (3) the small number of changes made to data memory between synchronization steps. Furthermore, we observe that to obtain this limited factor of 10-fold speed-up, it is necessary to exploit parallelism at a very fine granularity. We propose that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/sec. This speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

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Global Multi-Threaded Instruction Scheduling 40

Global Multi-Threaded Instruction Scheduling

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Guilherme Ottoni David August Department of Computer Science Princeton University USA

ISBN: (纸本)9780769530475

The microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro-architectural limitations. Despite this move, CMPs do not directly improve the performance of single-threaded codes, a characteristic of most applications. In order to support parallelization of general-purpose applications, computer architects have proposed CMPs with lightweight scalar communication mechanisms (R. Rangan et al., 2004), (K. Sankaralingam, et al., 2003), (M.B. Taylor et al., 2005). Despite such support, most existing compiler multi-threading techniques have generally demonstrated little effectiveness in extracting parallelism from non-scientific applications (W. Lee et al., 1998), (W. Lee et al., 2002), (K. Rich and M. Farrens, 2004). The main reason for this is that such techniques are mostly restricted to extracting parallelism within straight-line regions of code. In this paper, we first propose a framework that enables global multi-threaded instruction scheduling in general. We then describe GREMIO, a scheduler built using this framework. GREMIO operates at a global scope, at the procedure level, and uses control dependence analysis to extract non-speculative thread-level parallelism from sequential codes. Using a fully automatic compiler implementation of GREMIO and a validated processor model, this paper demonstrates gains for a dual-core CMP model running a variety of codes. Our experiments demonstrate the advantage of exploiting global scheduling for multithreaded architectures, and present gains in a detailed comparison with the decoupled software pipelining (DSWP) multi-threading technique (G. Ottoni et al., 2005). Furthermore, our experiments show that adding GREMIO to a compiler with DSWP improves the average speedup from 16.5% to 32.8% for important benchmark functions when utilizing two cores, indicating the importance of this technique in making compilers extract threa

关键词： Job shop scheduling Processor scheduling Application software parallel processing Microprocessors Computer applications Concurrent computing Automatic control Computer architecture Pipeline processing

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A deterministic parallel APSP algorithm and its applications 21

A deterministic parallel APSP algorithm and its applications

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Adam Karczmarz Piotr Sankowski University of Warsaw Poland

ISBN: (纸本)9781611976465

In this paper we show a deterministic parallel all-pairs shortest paths algorithm for real-weighted directed graphs. The algorithm has Õ(nm + (n/d)3) work and Õ(d) depth for any depth parameter d ∈ [1, n]. To the best of our knowledge, such a trade-off has only been previously described for the real-weighted single-source shortest paths problem using randomization [Bringmann et al., ICALP'17]. Moreover, our result improves upon the parallelism of the state-of-the-art randomized parallel algorithm for computing transitive closure, which has Õ(nm + n3/d2) work and Õ(d) depth [Ullman and Yannakakis, SIAM J. Comput. '91].Our APSP algorithm turns out to be a powerful tool for designing efficient planar graph algorithms in both parallel and sequential regimes. By suitably adjusting the depth parameter d and applying known techniques, we obtain:(1) nearly work-efficient Õ(n1/6)-depth parallel algorithms for the real-weighted single-source shortest paths problem and finding a bipartite perfect matching in a planar graph,(2) an Õ(n9/8)-time sequential strongly polynomial algorithm for computing a minimum mean cycle or a minimum cost-to-time-ratio cycle of a planar graph,(3) a slightly faster algorithm for computing so-called external dense distance graphs of all pieces of a recursive decomposition of a planar *** notable ingredient of our parallel APSP algorithm is a simple deterministic Õ(nm)-work Õ(d)-depth procedure for computing Õ(n/d)-size hitting sets of shortest d-hop paths between all pairs of vertices of a real-weighted digraph. Such hitting sets have also been called d-hub sets. Hub sets have previously proved especially useful in designing parallel or dynamic shortest paths algorithms and are typically obtained via random sampling. Our procedure implies, for example, an Õ(nm)-time deterministic algorithm for finding a shortest negative cycle of a real-weighted digraph. Such a near-optimal bound for this problem has been so far only achieved using a randomize

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parallel algorithms for the transitive closure and the connected component problems 76

Parallel algorithms for the transitive closure and the conne...

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Proceedings of the eighth annual acm symposium on Theory of computing

作者： D. S. Hirschberg

ISBN: (纸本)9781450374149

parallel programs are presented that determine the transitive closure of a matrix using n3 processors and connected components of an undirected graph using n2 processors. In both cases, the desired results are obtained in time 0(log2n). It is assumed that the processors have access to common memory. Simultaneous access to the same location is permitted for fetch, but not store, *** problem of determining the connected components of a graph using a parallel computer has recently appeared in the literature [1,2]. The result in [1] is based on finding the transitive closure of a matrix in time 0(log2n) which can be done using 0(n3) processors. We show that n2 processors are sufficient to solve the connected component problem in time 0(log2n).We present algorithm CLOSURE that will find the transitive closure of Boolean matrix M [n by n] using n3 processors [numbered P(0,0,0) through P(n−1 ,n−1, n−1)] each of which has local memory and each of which can access common array A [n by n].

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An Exponential Speedup in parallel Running Time for Submodular Maximization without Loss in Approximation 19

An Exponential Speedup in Parallel Running Time for Submodul...

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annual acm-SIAM symposium on Discrete algorithms

作者： Eric Balkanski Aviad Rubinstein Yaron Singer Harvard University

In this paper we study the adaptivity of submodular maximization. Adaptivity quantifies the number of sequential rounds that an algorithm makes when function evaluations can be executed in parallel. Adaptivity is a fundamental concept that is heavily studied across a variety of areas in computer science, largely due to the need for parallelizing computation. For the canonical problem of maximizing a monotone submodular function under a cardinality constraint, it is well known that a simple greedy algorithm achieves a 1 - 1/e approximation [NWF78] and that this approximation is optimal for polynomial-time algorithms [NW78]. Somewhat surprisingly, despite extensive efforts on submodular optimization for large-scale datasets, until very recently there was no known algorithm that achieves a constant factor approximation for this problem whose adaptivity is sublinear in the size of the ground set n. Recent work by [BS18] describes an algorithm that obtains an approximation arbitrarily close to 1/3 in O(log n) adaptive rounds and shows that no algorithm can obtain a constant factor approximation in o(log n) adaptive rounds. This approach achieves an exponential speedup in adaptivity (and parallel running time) at the expense of approximation quality. In this paper we describe a novel approach that yields an algorithm whose approximation is arbitrarily close to the optimal 1 - 1/e guarantee in O(log n) adaptive rounds. This algorithm therefore achieves an exponential speedup in parallel running time for submodular maximization at the expense of an arbitrarily small loss in approximation quality. This guarantee is optimal in both approximation and adaptivity, up to lower order terms.

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Optimal simulations of tree machines

Optimal simulations of tree machines

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annual IEEE symposium on Foundations of Computer Science

作者： Sandeep Bhatt Fan Chung Tom Leighton Arnold Rosenberg Department Computer Science Yale University New Heaven CT USA Bell Communications Research Inc. Morristown NJ USA Department Mathematics M.I.T. Cambridge MA USA Department Computer Science University of Massachusetts Amherst MA USA

Universal networks offer the advantage that they can execute programs written for simpler architectures without significant run-time overhead. In this paper we investigate simulations of tree machines; the fact that divide-and-conquer algorithms are programmed naturally on trees motivates our investigation. Among various proposals for parallel computing the boolean hypercube has emerged as a particularly versatile network. It is well known that programs for multidimensional grid machines, for example, can be executed on a hypercube with no communications overhead by embedding the grid as a subgraph of the hypercube. Our first result is that a program for any tree machine can be executed on the hypercube with constant overhead. More precisely, every cycle of a synchronous binary tree can be simulated in O(1) cycles on a hypercube, independent of the shape of the tree. The algorithm to embed the tree within the hypercube runs in polynomial time. We also give efficient simulations of arbitrary binary trees on the complete binary tree, the FFT and shuffle-exchange networks. It is natural to ask if any sparse network can simulate every binary tree efficiently. Somewhat surprisingly, we construct a universal bounded-degree network on N nodes for which every N node binary tree is a spanning tree. In other words, every binary tree can be simulated on our universal network with no overhead. This improves previous bounds on the sizes of universal graphs for trees.

关键词： Hypercubes Binary trees Computational modeling Tree graphs Computer architecture Runtime Proposals parallel processing Multidimensional systems Shape

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Sparsifying Distributed algorithms with Ramifications in Massively parallel Computation and Centralized Local Computation 19

Sparsifying Distributed Algorithms with Ramifications in Mas...

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annual acm-SIAM symposium on Discrete algorithms

作者： Mohsen Ghaffari Jara Uitto ETH Zurich ETH Zurich & U. of Freiburg

We introduce a method for "sparsifying" distributed algorithms and exhibit how it leads to improvements that go past known barriers in two algorithmic settings of large-scale graph processing: Massively parallel Computation (MPC), and Local Computation algorithms (LCA).· MPC with Strongly Sublinear Memory: Recently, there has been growing interest in obtaining MPC algorithms that are faster than their classic O(log n)-round parallel (PRAM) counterparts for problems such as Maximal Independent Set (MIS), Maximal Matching, 2-Approximation of Minimum Vertex Cover, and (1 + ε)-Approximation of Maximum Matching. Currently, all such MPC algorithms require memory of Ω(n) per machine: Czumaj. [STOC'18] were the first to handle Ω(n) memory, running in O((log log n)~2) rounds, who improved on the n~(1+Ω(1)) memory requirement of the O(1)-round algorithm of Lattanzi [SPAA'11]. We obtain O(√log Δ)-round MPC algorithms for all these four problems that work even when each machine has strongly sublinear memory, e.g., n~a for any constant a ∈ (0,1). Here, A denotes the maximum degree. These are the first sublogarithmic-time MPC algorithms for (the general case of) these problems that break the linear memory barrier.· LCAs with Query Complexity Below the Parnas-Ron Paradigm: Currently, the best known LCA for MIS has query complexity Δ~(O(logΔ)) poly(log n), by Ghaffari [SODA'16], which improved over the Δ~(O(log2 Δ)) poly(log n) bound of Levi. [Algorithmica'17]. As pointed out by Rubinfeld, obtaining a query complexity of poly(Δ log n) remains a central open question. Ghaffari's bound almost reaches a Δ~(Ω(log Δ/log log Δ)) barrier common to all known MIS LCAs, which simulate a distributed algorithm by learning the full local topology, a la Parnas-Ron [TCS'07]. There is a barrier because the distributed complexity of MIS has a lower bound of Ω~((log Δ)/(log log Δ)), by results of Kuhn, [Jacm'16], which means this methodology cannot go below query complexity Δ~(Ω(log Δ)/(log log Δ)).

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Race detection and reachability in nearly series-parallel DAGs 18

Race detection and reachability in nearly series-parallel DA...

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Proceedings of the Twenty-Ninth annual acm-SIAM symposium on Discrete algorithms

作者： Kunal Agrawal Joseph Devietti Jeremy T. Fineman I-Ting Angelina Lee Robert Utterback Changming Xu Washington University in St. Louis University of Pennsylvania Georgetown University

ISBN: (纸本)9781611975031

A program is said to have a determinacy race if logically parallel parts of a program access the same memory location and one of the accesses is a write. These races are generally bugs in the program since they lead to non-deterministic program behavior --- different schedules of the program can lead to different results. Most prior work on detecting these races focuses on a subclass of programs with series-parallel or nested *** paper presents a race-detection algorithm for detecting races in a more general class of programs, namely programs that include arbitrary ordering constraints in additional to the series-parallel constructs. The algorithm performs a serial execution of the program, augmented to detect races, in O(T1 + k2) time, where T1 is the sequential running time of the original program and k is the number of non series-parallel *** main technical novelty of this paper is a new data structure, R-Sketch, for answering reachability queries in nearly series-parallel (SP) directed acyclic graphs (DAGs). Given as input a graph comprising an n-node series parallel graph and k additional non-SP edges, the total construction time of the data structure is O(n + k2), and each reachability query can be answered in O(1) time. The data structure is traversally incremental, meaning that it supports the insertion of nodes/edges, but only as they are discovered through a graph traversal.

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