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A Configurable Cloud-Scale DNN Processor for Real-Time AI

A Configurable Cloud-Scale DNN Processor for Real-Time AI

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annual International symposium on Computer Architecture, ISCA

作者： Jeremy Fowers Kalin Ovtcharov Michael Papamichael Todd Massengill Ming Liu Daniel Lo Shlomi Alkalay Michael Haselman Logan Adams Mahdi Ghandi Stephen Heil Prerak Patel Adam Sapek Gabriel Weisz Lisa Woods Sitaram Lanka Steven K. Reinhardt Adrian M. Caulfield Eric S. Chung Doug Burger Microsoft

Interactive AI-powered services require low-latency evaluation of deep neural network (DNN) models-aka ""real-time AI"". The growing demand for computationally expensive, state-of-the-art DNNs, coupled with diminishing performance gains of general-purpose architectures, has fueled an explosion of specialized Neural Processing Units (NPUs). NPUs for interactive services should satisfy two requirements: (1) execution of DNN models with low latency, high throughput, and high efficiency, and (2) flexibility to accommodate evolving state-of-the-art models (e.g., RNNs, CNNs, MLPs) without costly silicon updates. This paper describes the NPU architecture for Project Brainwave, a production-scale system for real-time AI. The Brainwave NPU achieves more than an order of magnitude improvement in latency and throughput over state-of-the-art GPUs on large RNNs at a batch size of 1. The NPU attains this performance using a single-threaded SIMD ISA paired with a distributed microarchitecture capable of dispatching over 7M operations from a single instruction. The spatially distributed microarchitecture, scaled up to 96,000 multiply-accumulate units, is supported by hierarchical instruction decoders and schedulers coupled with thousands of independently addressable high-bandwidth on-chip memories, and can transparently exploit many levels of fine-grain SIMD parallelism. When targeting an FPGA, microarchitectural parameters such as native datapaths and numerical precision can be "synthesis specialized" to models at compile time, enabling atypically high FPGA performance competitive with hardened NPUs. When running on an Intel Stratix 10 280 FPGA, the Brainwave NPU achieves performance ranging from ten to over thirty-five teraflops, with no batching, on large, memory-intensive RNNs.

关键词： Field programmable gate arrays Computer architecture Throughput parallel processing Real-time systems Microarchitecture Computational modeling

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Memory models: a case for rethinking parallel languages and hardware 09

Memory models: a case for rethinking parallel languages and ...

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Proceedings of the twenty-first annual symposium on parallelism in algorithms and architectures

作者： Sarita V. Adve University of Illinois at Urbana-Champaign Urbana IL USA

ISBN: (纸本)9781605586069

The era of parallel computing for the masses is here, but writing correct parallel programs remains a challenge--popular parallel environments offer no analogs for the concepts of structured and safe sequential programming. The memory model forms the heart of the concurrency semantics of any (shared-memory) parallel language or hardware. Unfortunately, it has involved a tradeoff between programmability and performance, and has arguably been one of the most challenging and contentious areas in shared-memory specification. Recent broad community-scale efforts have finally led to a convergence in this debate, with popular languages such as Java and C++ and most hardware vendors publishing compatible memory model specifications. Although this convergence is a dramatic improvement, it has exposed fundamental shortcomings in current popular languages and systems that prevent achieving the vision of structured and safe parallel programming.I will discuss the path to the above convergence, the hard lessons learned, and their implications. A cornerstone of this convergence has been the view that the memory model should be a contract between the programmer and the system--if the programmer writes well-structured (data-race-free) programs, the system will provide high programmability (sequential consistency) and performance. I will discuss why this view is the best we can do with current popular languages, and why it should be unacceptable moving forward. I will then discuss research directions that eliminate worrying about the memory model, but require rethinking popular parallel languages and hardware. In particular, I will argue for languages that eliminate data races by design and provide determinism by default, while retaining the advantages of modern object-oriented programming. I will also argue for hardware that takes advantage of such disciplined programming models to enable energy-efficient performance scalability. I will use the Deterministic parallel Java language

关键词： memory models memory consistency models safe programming multicore architecture

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sNPU: Trusted Execution Environments on Integrated NPUs

sNPU: Trusted Execution Environments on Integrated NPUs

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annual International symposium on Computer Architecture, ISCA

作者： Erhu Feng Dahu Feng Dong Du Yubin Xia Haibo Chen Institute of Parallel and Distributed Systems SEIEE Shanghai Jiao Tong University Department of Precision Instrument Tsinghua University Engineering Research Center for Domain-specific Operating Systems Ministry of Education China Key Laboratory of System Software (Chinese Academy of Sciences)

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Trusted execution environment (TEE) promises strong security guarantee with hardware extensions for security-sensitive tasks. Due to its numerous benefits, TEE has gained widespread adoption, and extended from CPU-only TEEs to FPGA and GPU TEE systems. However, existing TEE systems exhibit inadequate and inefficient support for an emerging (and significant) processing unit, NPU. For instance, commercial TEE systems resort to coarse-grained and static protection approaches for NPUs, resulting in notable performance degradation (10%–20%), limited (or no) multitasking capabilities, and suboptimal resource utilization. In this paper, we present a secure NPU architecture, known as sNPU, which aims to mitigate vulnerabilities inherent to the design of NPU architectures. First, sNPU proposes NPU Guarder to enhance the NPU’s access control. Second, sNPU defines new attack surfaces leveraging in-NPU structures like scratchpad and NoC, and designs NPU Isolator to guarantee the isolation of scratchpad and NoC routing. Third, our system introduces a trusted software module called NPU Monitor to minimize the software TCB. Our prototype, evaluated on FPGA, demonstrates that sNPU significantly mitigates the runtime costs associated with security checking (from upto 20% to 0%) while incurring less than 1% resource costs.

关键词： Costs Runtime Prototypes Computer architecture Routing Software Resource management

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Tight bounds for parallel randomized load balancing: extended abstract 11

Tight bounds for parallel randomized load balancing: extende...

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Proceedings of the forty-third annual acm symposium on Theory of computing

作者： Christoph Lenzen Roger Wattenhofer ETH Zurich Zurich Switzerland

ISBN: (纸本)9781450306911

We explore the fundamental limits of distributed balls-into-bins algorithms, i.e., algorithms where balls act in parallel, as separate agents. This problem was introduced by Adler et al., who showed that non-adaptive and symmetric algorithms cannot reliably perform better than a maximum bin load of Theta(log log n / log log log n) within the same number of rounds. We present an adaptive symmetric algorithm that achieves a bin load of two in log* n+O(1) communication rounds using O(n) messages in total. Moreover, larger bin loads can be traded in for smaller time complexities. We prove a matching lower bound of (1-o(1))log* n on the time complexity of symmetric algorithms that guarantee small bin loads at an asymptotically optimal message complexity of O(n). The essential preconditions of the proof are (i) a limit of O(n) on the total number of messages sent by the algorithm and (ii) anonymity of bins, i.e., the port numberings of balls are not globally consistent. In order to show that our technique yields indeed tight bounds, we provide for each assumption an algorithm violating it, in turn achieving a constant maximum bin load in constant *** an application, we consider the following problem. Given a fully connected graph of n nodes, where each node needs to send and receive up to n messages, and in each round each node may send one message over each link, deliver all messages as quickly as possible to their destinations. We give a simple and robust algorithm of time complexity O(log* n) for this task and provide a generalization to the case where all nodes initially hold arbitrary sets of messages. Completing the picture, we give a less practical, but asymptotically optimal algorithm terminating within O(1) rounds. All these bounds hold with high probability.

关键词： asymptotic bounds load balancing randomized allocation

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pLUTo: Enabling Massively parallel Computation in DRAM via Lookup Tables 22

pLUTo: Enabling Massively Parallel Computation in DRAM via L...

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Proceedings of the 55th annual IEEE/acm International symposium on Microarchitecture

作者： João Dinis Ferreira Gabriel Falcao Juan Gómez-Luna Mohammed Alser Lois Orosa Mohammad Sadrosadati Jeremie S. Kim Geraldo F. Oliveira Taha Shahroodi Anant Nori Onur Mutlu ETH Zürich IT University of Coimbra ETH Zürich and Galicia Supercomputing Center TU Delft Intel

ISBN: (纸本)9781665462723

Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottleneck can be alleviated using Processing-in-Memory (PiM). One category of PiM is Processing-using-Memory (PuM), in which computation takes place inside the memory array by exploiting intrinsic analog properties of the memory device. PuM yields high performance and energy efficiency, but existing PuM techniques support a limited range of operations. As a result, current PuM architectures cannot efficiently perform some complex operations (e.g., multiplication, division, exponentiation) without large increases in chip area and design *** overcome these limitations of existing PuM architectures, we introduce pLUTo (processing-using-memory with lookup table (LUT) operations), a DRAM-based PuM architecture that leverages the high storage density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). The key idea of pLUTo is to replace complex operations with low-cost, bulk memory reads (i.e., LUT queries) instead of relying on complex extra *** evaluate pLUTo across 11 real-world workloads that showcase the limitations of prior PuM approaches and show that our solution outperforms optimized CPU and GPU baselines by an average of 713× and 1.2×, respectively, while simultaneously reducing energy consumption by an average of 1855× and 39.5×. Across these workloads, pLUTo outperforms state-of-the-art PiM architectures by an average of 18.3×. We also show that different versions of pLUTo provide different levels of flexibility and performance at different additional DRAM area overheads (between 10.2% and 23.1%). pLUTo's source code and all scripts required to reproduce the results of this paper are openly and fully available at https://***/CMU-SAFARI/pLUTo.

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The predictability of branches in libraries

The predictability of branches in libraries

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： B. Calder D. Grunwald A. Srivastava Department of Computer Science University of Colorado Boulder CO USA Western Research Laboratory Digital Equipment Corporation Palo Alto CA USA

Profile-based optimizations are being used with increasing frequency. Profile information can be used to improve instruction scheduling, code layout, and to increase instruction level parallelism. These optimizations have been shown to be effective when they are applied to the same program from which the profile was gathered. However it is an open question how profile-based optimizations should be applied to library subroutines. If many programs use libraries in the same way, it may be possible to "preoptimize" a library or to use an optimized shared library. This study examines the use of commonly used libraries among 43 C and FORTRAN programs to see if the libraries have common behavior across different programs. We examine the behavior of the most commonly used Unix libraries on Digital Unix. We found that libraries have very predictable behavior between applications. This implies that profile-based compiler optimizations may be effective far libraries across different applications. Therefore, one can use profile optimizations on shared and non-shared libraries before they are shipped, allowing a program using those libraries to take advantage of profile-based optimizations without having to gather any profiles. All results in this study are shown using branch misprediction rates. We feel this metric indicates the likelihood that programs have similar behavior and allows comparison to earlier branch prediction studies.

关键词： Software libraries Optimizing compilers Application software Computer science Frequency Processor scheduling parallel processing algorithms Programming profession Accuracy

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Software Transactional Memory for GPU architectures 14

Software Transactional Memory for GPU Architectures

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Proceedings of annual IEEE/acm International symposium on Code Generation and Optimization

作者： Yunlong Xu Rui Wang Nilanjan Goswami Tao Li Lan Gao Depei Qian School of Electronic and Information Engineering Xi'an Jiaotong University Xi'an China School of Computer Science and Engineering Beihang University Beijing China ECE Department University of Florida Gainesville USA School of Electronic and Information Engineering Xi'an Jiaotong University Xi'an China and School of Computer Science and Engineering Beihang University Beijing China

ISBN: (纸本)9781450326704

Modern GPUs have shown promising results in accelerating computation intensive and numerical workloads with limited dynamic data sharing. However, many real-world applications manifest ample amount of data sharing among concurrently executing threads. Often data sharing requires mutual exclusion mechanism to ensure data integrity in multithreaded environment. Although modern GPUs provide atomic primitives that can be leveraged to construct fine-grained locks, lock-based synchronization requires significant programming efforts to achieve functional correctness. The massive multithreading and SIMT execution paradigm of GPUs further extend the challenges of GPU *** make applications with dynamic data sharing benefit from GPU acceleration, we propose a novel software transactional memory system for GPU architectures (GPU-STM). The major challenges include ensuring good scalability with respect to the massive multithreading of GPUs, and preventing livelocks caused by the SIMT execution paradigm of GPUs. To this end, we propose (1) a hierarchical validation technique and (2) an encounter-time lock-sorting mechanism to deal with the two challenges, respectively. We build our GPU-STM prototype based on the commercially available GPU platform and runtime. Our real system based evaluation shows that GPU-STM outperforms coarse-grain locks on GPUs by up to 20x.

关键词： Software Transactional Memory parallel Programming General-Purpose GPU Computing

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Delaunay graphs of point sets in the plane with respect to axis-parallel rectangles 08

Delaunay graphs of point sets in the plane with respect to a...

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Proceedings of the nineteenth annual acm-SIAM symposium on Discrete algorithms

作者： Xiaomin Chen János Pach Mario Szegedy Gábor Tardos Google New York NY City College CUNY and Courant Institute NYU New York NY Rutgers University NJ Simon Fraser University Burnaby B.C. Canada and Rényi Institute Reáltanoda utca Hungary

Given a point set P in the plane, the Delaunay graph with respect to axis-parallel rectangles is a graph defined on the vertex set P, whose two points p,q ∈ P are connected by an edge if and only if there is a rectangle parallel to the coordinate axes that contains p and q, but no other elements of P. The following question of Even et al. [ELRS03] was motivated by a frequency assignment problem in cellular telephone networks. Does there exist a constant c > 0 such that the Delaunay graph of any set of n points in general position in the plane contains an independent set of size at least cn? We answer this question in the negative, by proving that the largest independent set in a randomly and uniformly selected point set in the unit square is O(n log2 log n/log n), with probability tending to 1. We also show that our bound is not far from optimal, as the Delaunay graph of a uniform random set of n points almost surely has an independent set of size at least cn/ log *** give two further applications of our methods. 1. We construct 2-dimensional n-element partially ordered sets such that the size of the largest independent sets of vertices in their Hasse diagrams is o(n). This answers a question of Matoušek and Přívětivý [MaP06] and improves a result of Kříž and Nešetřil [KrN91]. 2. For any positive integers c and d, we prove the existence of a planar point set with the property that no matter how we color its elements by c colors, we find an axis-parallel rectangle containing at least d points, all of which have the same color. This solves an old problem from [BrMP05].

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NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing

NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nea...

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annual International symposium on Computer Architecture, ISCA

作者： Yitu Wang Shiyu Li Qilin Zheng Linghao Song Zongwang Li Andrew Chang Hai “Helen” Li Yiran Chen Duke University Durham North Carolina USA University of California Los Angeles California USA Samsung Semiconductor Inc. San Jose California USA

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Approximate nearest neighbor search (ANNS) is a key retrieval technique for vector database and many data center applications, such as person re-identification and recommendation systems. It is also fundamental to retrieval augmented generation (RAG) for large language models (LLM) now. Among all the ANNS algorithms, graph-traversal-based ANNS achieves the highest recall rate. However, as the size of dataset increases, the graph may require hundreds of gigabytes of memory, exceeding the main memory capacity of a single workstation node. Although we can do partitioning and use solid-state drive (SSD) as the backing storage, the limited SSD I/O bandwidth severely degrades the performance of the system. To address this challenge, we present NDSEARCh, a hardware-software co-designed near-data processing (NDP) solution for ANNS processing. NDSeARCH consists of a novel in-storage computing architecture, namely, SEARSSD, that supports the ANNS kernels and leverages logic unit (LUN)-level parallelism inside the NAND flash chips. NDSEARCH also includes a processing model that is customized for NDP and cooperates with SearSSD. The processing model enables us to apply a two-level scheduling to improve the data locality and exploit the internal bandwidth in NDSearch, and a speculative searching mechanism to further accelerate the ANNS workload. Our results show that NDSEARCH improves the throughput by up to $31.7 \times, 14.6 \times, 7.4 \times 2.9 \times$ over CPU, GPU, a state-of-the-art SmartSSD-only design, and DeepStore, respectively. NDSEARCH also achieves two orders-of-magnitude higher energy efficiency than CPU and GPU.

关键词： Computational modeling Memory management Graphics processing units Bandwidth parallel processing Nearest neighbor methods Throughput

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Executing dynamic data-graph computations deterministically using chromatic scheduling 14

Executing dynamic data-graph computations deterministically ...

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Proceedings of the 26th acm symposium on parallelism in algorithms and architectures

作者： Tim Kaler William Hasenplaugh Tao B. Schardl Charles E. Leiserson MIT CSAIL Cambridge MA USA

ISBN: (纸本)9781450328210

A data-graph computation — popularized by such programming systems as Galois, Pregel, GraphLab, PowerGraph, and GraphChi — is an algorithm that performs local updates on the vertices of a graph. During each round of a data-graph computation, an update function atomically modifies the data associated with a vertex as a function of the vertex's prior data and that of adjacent vertices. A dynamic data-graph computation updates only an active subset of the vertices during a round, and those updates determine the set of active vertices for the next *** paper introduces PRISM, a chromatic-scheduling algorithm for executing dynamic data-graph computations. PRISM uses a vertex-coloring of the graph to coordinate updates performed in a round, precluding the need for mutual-exclusion locks or other nondeterministic data synchronization. A multibag data structure is used by PRISM to maintain a dynamic set of active vertices as an unordered set partitioned by color. We analyze PRISM using work-span analysis. Let G=(V,E) be a degree-Δ graph colored with Χ colors, and suppose that Q⊆V is the set of active vertices in a round. Define size(Q)=[Q] + Σv∈Qdeg(v), which is proportional to the space required to store the vertices of Q using a sparse-graph layout. We show that a P-processor execution of PRISM performs updates in Q using O(Χ(lg (Q/Χ)+lgΔ)+ lgP) span and Θ(size(Q)+Χ+P) work. These theoretical guarantees are matched by good empirical performance. We modified GraphLab to incorporate PRISM and studied seven application benchmarks on a 12-core multicore machine. PRISM executes the benchmarks 1.2–2.1 times faster than GraphLab's nondeterministic lock-based scheduler while providing deterministic *** paper also presents PRISM-R, a variation of PRISM that executes dynamic data-graph computations deterministically even when updates modify global variables with associative operations. PRISM-R satisfies the same theoretical bounds as PRISM, but its implementation is

关键词： determinism reducers multithreading parallel programming work stealing data-graph computations chromatic scheduling multicore

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