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annual acm symposium on parallelism in algorithms and architectures

Annual ACM symposium on parallelism in algorithms and archit...

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30th acm symposium on parallelism in algorithms and architectures, SPAA 2018

ISBN: (纸本)9781450357999

The proceedings contain 47 papers. The topics discussed include: parallel minimum cuts in near-linear work and low depth;trees for vertex cuts, hypergraph cuts and minimum hypergraph bisection;dynamic representations of sparse distributed networks: a locality-sensitive approach;constant-depth and subcubic-size threshold circuits for matrix multiplication;integrated model, batch, and domain parallelism in training neural networks;brief announcement: on approximating pagerank locally with sublinear query complexity;brief announcement: coloring-based task mapping for dragonfly systems;brief announcement: parallel transitive closure within 3D crosspoint memory;and lock-free contention adapting search trees.

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Analysis of on-chip communication properties in accelerator architectures for Deep Neural Networks

Analysis of on-chip communication properties in accelerator ...

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International symposium on Networks-on-Chip (NOCS)

作者： Hana Krichene Jean-Marc Philippe Université Paris-Saclay Palaiseau France

ISBN: (纸本)9781665417228

Deep neural networks (DNNs) algorithms are expected to be core components of next-generation applications. These high performance sensing and recognition algorithms are key enabling technologies of smarter systems that make appropriate decisions about their environment. The integration of these compute-intensive and memory-hungry algorithms into embedded systems will require the use of specific energy-efficient hardware accelerators. The intrinsic parallelism of DNNs algorithms allows for the use of a large number of small processing elements, and the tight exploitation of data reuse can significantly reduce power consumption. To meet these features, many dataflow models and on-chip communication proposals have been studied in recent years. This paper proposes a comprehensive study of on-chip communication properties based on the analysis of application-specific features, such as data reuse and communication models, as well as the results of mapping these applications to architectures of different sizes. In addition, the influence of mechanisms such as broadcast and multicast on performance and energy efficiency is analyzed. This study leads to the definition of overarching features to be integrated into next-generation on-chip communication infrastructures for CNN accelerators.

关键词： Deep learning Power demand Network-on-chip parallel processing Energy efficiency Sensors Convolutional neural networks

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Privacy Preserving Cooperative Computation for Personalized Web Search Applications 20

Privacy Preserving Cooperative Computation for Personalized ...

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35th annual acm symposium on Applied Computing (SAC)

作者： Kaaniche, Nesrine Masmoudi, Souha Znina, Souha Laurent, Maryline Demir, Levent Univ Sheffield Dept Comp Sci Sheffield S Yorkshire England Inst Polytech Paris Telecom SudParis Evry France Inst Polytech Paris Telecom SudParis Chair Values & Policies Personal Informat SAMOVAR Evry France Qwant Res Paris France

ISBN: (纸本)9781450368667

With the emergence of connected objects and the development of Artificial Intelligence (AI) mechanisms and algorithms, personalized applications are gaining an expanding interest, providing services tailored to each single user needs and expectations. They mainly rely on the massive collection of personal data generated by a large number of applications hosted from different connected devices. In this paper, we present CoWSA, a privacy preserving Cooperative computation framework for personalized Web Search peripheral Applications. The proposed framework is multi-fold. First, it provides the empowerment to end-users to control the disclosed personal data to third parties, while leveraging the trade-off between privacy and utility. Second, as a decentralized solution, CoWSA mitigates single points of failures, while ensuring the security of queries, the anonymity of submitting users, and the incentive of contributing nodes. Third, CoWSA is scalable as it provides acceptable computation and communication costs compared to most closely related schemes.

关键词： privacy web search engines personalized services collaborative computation decentralized architectures Interest-based networks

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SOFF: An OpenCL High-Level Synthesis Framework for FPGAs 20

SOFF: An OpenCL High-Level Synthesis Framework for FPGAs

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47th acm/IEEE annual International symposium on Computer Architecture (ISCA)

作者： Jo, Gangwon Kim, Heehoon Lee, Jeesoo Lee, Jaejin ManyCoreSoft Seoul 08826 South Korea Seoul Natl Univ Dept Comp Sci & Engn Seoul 08826 South Korea

ISBN: (纸本)9781728146614

Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor performance and usability. This paper proposes a high-level synthesis framework of OpenCL for FPGAs, called SOFF. It automatically synthesizes a datapath to execute many OpenCL kernel threads in a pipelined manner. It also synthesizes an efficient memory subsystem for the datapath based on the characteristics of OpenCL kernels. Unlike previous high-level synthesis techniques, we propose a formal way to handle variable-latency instructions, complex control flows, OpenCL barriers, and atomic operations that appear in real-world OpenCL kernels. SOFF is the first OpenCL framework that correctly compiles and executes all applications in the SPEC ACCEL benchmark suite except three applications that require more FPGA resources than are available. In addition, SOFF achieves the speedup of 1.33 over Intel FPGA SDK for OpenCL without any explicit user annotation or source code modification.

关键词： Accelerator architectures FPGAs high level synthesis parallel programming pipeline processing

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Proceedings of the 11th Workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

Proceedings of the 11th Workshop on Parallel Programming and...

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8th International symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017

ISBN: (纸本)9781450375450

The proceedings contain 5 papers. The topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modeling in embedded GPUs with dynamic voltage and frequency scaling;fault-tolerant online scheduling algorithms for CubeSats;an OpenMP parallel genetic algorithm for design space exploration of heterogeneous multi-processor embedded systems;and automated precision tuning in activity classification systems: a case study.

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A time-optimal randomized parallel algorithm for MIS 21

A time-optimal randomized parallel algorithm for MIS

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Mohsen Ghaffari Bernhard Haeupler ETH Zurich Carnegie Mellon University

ISBN: (纸本)9781611976465

We present a randomized parallel algorithm, in the Exclusive-Read Exclusive-Write (EREW) PRAM model, that computes a Maximal Independent Set (MIS) in O(log n) time and using O(m log2 n) work, with high probability. Thus, MIS ∈ RNC1. This time complexity is optimal and it improves on the celebrated O(log2 n) time algorithms of Luby [STOC'85] and Alon, Babai, and Itai [JALG'86], which had remained the state of the art for the past 35 years.

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Dynamic graph algorithms with batch updates in the massively parallel computation model 21

Dynamic graph algorithms with batch updates in the massively...

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Krzysztof Nowicki Krzysztof Onak University of Wroclaw and IBM T.J. Watson Research Center IBM Research

ISBN: (纸本)9781611976465

We study dynamic graph algorithms in the Massively parallel Computation model, which was inspired by practical data processing systems. Our goal is to provide algorithms that can efficiently handle large batches of edge insertions and *** show algorithms that require fewer rounds to update a solution to problems such as Minimum Spanning Forest, 2-Edge Connected Components, and Maximal Matching than would be required by their static counterparts to compute it from scratch. They work in the most restrictive memory regime, in which local memory per machine is strongly sublinear in the number of graph vertices. Improving on the size of the batch they can handle efficiently would improve on the round complexity of known static algorithms on sparse *** algorithms can process batches of updates of size Θ(S), for Minimum Spanning Forest and 2-Edge Connected Components, and Θ(S1−ϵ), for Maximal Matching, in O(1) rounds, where S is the local memory of a single machine.

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Deterministic Atomic Buffering 53

Deterministic Atomic Buffering

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53rd annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Chou, Yuan Hsi Ng, Christopher Cattell, Shaylin Intan, Jeremy Sinclair, Matthew D. Devietti, Joseph Rogers, Timothy G. Aamodt, Tor M. Univ British Columbia Vancouver BC Canada Univ Wisconsin Madison WI 53706 USA Univ Penn Philadelphia PA 19104 USA Purdue Univ W Lafayette IN 47907 USA AMD Res Santa Clara CA USA

ISBN: (纸本)9781728173832

Deterministic execution for GPUs is a desirable property as it helps with debuggability and reproducibility. It is also important for safety regulations, as safety critical workloads are starting to be deployed onto GPUs. Prior deterministic architectures, such as GPUDet, attempt to provide strong determinism for all types of workloads, incurring significant performance overheads due to the many restrictions that are required to satisfy determinism. We observe that a class of reduction workloads, such as graph applications and neural architecture search for machine learning, do not require such severe restrictions to preserve determinism. This motivates the design of our system, Deterministic Atomic Buffering (DAB), which provides deterministic execution with low area and performance overheads by focusing solely on ordering atomic instructions instead of all memory instructions. By scheduling atomic instructions deterministically with atomic buffering, the results of atomic operations are isolated initially and made visible in the future in a deterministic order. This allows the GPU to execute deterministically in parallel without having to serialize its threads for atomic operations as opposed to GPUDet. Our simulation results show that, for atomic-intensive applications, DAB performs 4x better than GPUDet and incurs only a 23% slowdown on average compared to a non-deterministic GPU architecture. We also characterize the bottlenecks and provide insights for future optimizations.

关键词： GPU architecture determinism performance parallel programming

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NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs 20

NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architectu...

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47th acm/IEEE annual International symposium on Computer Architecture (ISCA)

作者： Singh, Sonali Sarma, Anup Jao, Nicholas Pattnaik, Ashutosh Lu, Sen Yang, Kezhou Sengupta, Abhronil Narayanan, Vijaykrishnan Das, Chita R. Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA

ISBN: (纸本)9781728146614

Brain-inspired cognitive computing has so far followed two major approaches - one uses multi-layered artificial neural networks (ANNs) to perform pattern-recognition-related tasks, whereas the other uses spiking neural networks (SNNs) to emulate biological neurons in an attempt to be as efficient and fault-tolerant as the brain. While there has been considerable progress in the former area due to a combination of effective training algorithms and acceleration platforms, the latter is still in its infancy due to the lack of both. SNNs have a distinct advantage over their ANN counterparts in that they are capable of operating in an event-driven manner, thus consuming very low power. Several recent efforts have proposed various SNN hardware design alternatives, however, these designs still incur considerable energy overheads. In this context, this paper proposes a comprehensive design spanning across the device, circuit, architecture and algorithm levels to build an ultra low-power architecture for SNN and ANN inference. For this, we use spintronics-based magnetic tunnel junction (MTJ) devices that have been shown to function as both neuro-synaptic crossbars as well as thresholding neurons and can operate at ultra low voltage and current levels. Using this MTJbased neuron model and synaptic connections, we design a low power chip that has the flexibility to be deployed for inference of SNNs, ANNs as well as a combination of SNN-ANN hybrid networks - a distinct advantage compared to prior works. We demonstrate the competitive performance and energy efficiency of the SNNs as well as hybrid models on a suite of workloads. Our evaluations show that the proposed design, NEBULA, is up to 7.9x more energy efficient than a state-of-the-art design, ISAAC, in the ANN mode. In the SNN mode, our design is about 45x more energy-efficient than a contemporary SNN architecture, INXS. Power comparison between NEBULA ANN and SNN modes indicates that the latter is at least 6.25x more pow

关键词： Neural nets low power design domain-specific architectures memory technologies

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Tight bounds for parallel paging and green paging 21

Tight bounds for parallel paging and green paging

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Proceedings of the Thirty-Second annual acm-SIAM symposium on Discrete algorithms

作者： Kunal Agrawal Michael A. Bender Rathish Das William Kuszmaul Enoch Peserico Michele Scquizzato Washington University in St. Louis Stony Brook University MIT Università degli Studi di Padova Italy

ISBN: (纸本)9781611976465

In the parallel paging problem, there are p processors that share a cache of size k. The goal is to partition the cache among the processors over time in order to minimize their average completion time. For this long-standing open problem, we give tight upper and lower bounds of Θ(log p) on the competitive ratio with O(1) resource augmentation.A key idea in both our algorithms and lower bounds is to relate the problem of parallel paging to the seemingly unrelated problem of green paging. In green paging, there is an energy-optimized processor that can temporarily turn off one or more of its cache banks (thereby reducing power consumption), so that the cache size varies between a maximum size k and a minimum size k/p. The goal is to minimize the total energy consumed by the computation, which is proportional to the integral of the cache size over *** show that any efficient solution to green paging can be converted into an efficient solution to parallel paging, and that any lower bound for green paging can be converted into a lower bound for parallel paging, in both cases in a black-box fashion. We then show that, with O(1) resource augmentation, the optimal competitive ratio for deterministic online green paging is Θ(log p), which, in turn, implies the same bounds for deterministic online parallel paging.

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