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parallel rotor walks on finite graphs and applications in discrete load balancing 13

Parallel rotor walks on finite graphs and applications in di...

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

作者： Akbari, Hoda Berenbrink, Petra Simon Fraser University Burnaby BC Canada

ISBN: (纸本)9781450315722

We study the parallel rotor walk process, which works as follows: Consider a graph along with an arbitrary distribution of tokens over its nodes. Every node is equipped with a rotor that points to its neighbours in a fixed circular order each round, every node distributes all of its tokens using the rotor. One token is allocated to the neighbour pointed at by the rotor, then the rotor moves to the subsequent neighbour, and so on, until no token remains. The process can be considered as a deterministic analogue of a process in which tokens perform one independent random walk step in each round. We compare the distribution of tokens in the rotor walk process with expected distribution in the random walk model. The similarity between the two processes is measured by their discrepancy, which is the maximum difference between the corresponding distribution entries over all rounds and nodes. We analyze a lazy variation of rotor walks that simulates a random walk with loop probability of 1/2 on each node, and each node sends not all its tokens, but every other token in each round. Viewing the rotor walk as a load balancing process, we prove that the rotor walk falls in the class of bounded-error diffusion processes introduced in [H]. This gives us discrepancy bounds of Ο(log3/2 n) and Ο(1) for hypercube and r-dimensional torus with r = Ο(1), respectively, which improve over the best existing bounds of Ο(log 2 n) and Ο(n1/r). Also, as a result of switching to the load balancing view, we observe that the existing load balancing results can be translated to rotor walk discrepancy bounds not previously noticed in the rotor walk literature. We also use the idea of rotor walks to propose and analyze a randomized rounding discrete load balancing process that achieves the same balancing quality as similar protocols [11, 3], but uses fewer number of random bits compared to [3], and avoids the negative load problem of [11]. © 2013 acm.

关键词： Random processes

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Modeling communication in cache-coherent SMP systems - A case study with Xeon Phi

Modeling communication in cache-coherent SMP systems - A cas...

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22nd acm International symposium on High-Performance parallel and Distributed Computing, HPDC 2013

作者： Ramos, Sabela Hoefler, Torsten Computer Architecture Group University of A Coruña A Coruña Spain Scalable Parallel Computing Lab. ETH Zurich Zurich Switzerland

ISBN: (纸本)9781450319102

Most multi-core and some many-core processors implement cache coherency protocols that heavily complicate the design of optimal parallel algorithms. Communication is performed implicitly by cache line transfers between cores, complicating the understanding of performance properties. We developed an intuitive performance model for cache-coherent architectures and demonstrate its use with the currently most scalable cache-coherent many-core architecture, Intel Xeon Phi. Using our model, we develop several optimal and optimized algorithms for complex parallel data exchanges. All algorithms that were developed with the model beat the performance of the highly-tuned vendor-specific Intel OpenMP and MPI libraries by up to a factor of 4.3. The model can be simplified to satisfy the tradeoff between complexity of algorithm design and accuracy. We expect that our model can serve as a vehicle for advanced algorithm design. © 2013 acm.

关键词： Electronic data interchange

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Convergence and Scalarization for Data-parallel architectures

Convergence and Scalarization for Data-Parallel Architecture...

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11th IEEE/acm International symposium on Code Generation and Optimization (CGO)

作者： Lee, Yunsup Krashinsky, Ronny Grover, Vinod Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781467355254;9781467355247

Modern throughput processors such as GPUs achieve high performance and efficiency by exploiting data parallelism in application kernels expressed as threaded code. One draw-back of this approach compared to conventional vector architectures is redundant execution of instructions that are common across multiple threads, resulting in energy inefficiency due to excess instruction dispatch, register file accesses, and memory operations. This paper proposes to alleviate these overheads while retaining the threaded programming model by automatically detecting the scalar operations and factoring them out of the parallel code. We have developed a scalarizing compiler that employs convergence and variance analyses to statically identify values and instructions that are invariant across multiple threads. Our compiler algorithms are effective at identifying convergent execution even in programs with arbitrary control flow, identifying two-thirds of the opportunity captured by a dynamic oracle. The compile-time analysis leads to a reduction in instructions dispatched by 29%, register file reads and writes by 31%, memory address counts by 47%, and data access counts by 38%.

关键词： CUDA GPU Scalarization

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On-the-Fly Pipeline parallelism 13

On-the-Fly Pipeline Parallelism

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

作者： Lee, I.-Ting Angelina Leiserson, Charles E. Schardr, Tao B. Sukha, Jim Zhunping, Zhang MIT CSAIL 32 Vassar Street Cambridge MA 02139 United States Intel Corporation 25 Manchester Street Suite 200 Merrimack NH 03054 United States

ISBN: (纸本)9781450315722

Pipeline parallelism organizes a parallel program as a linear sequence of s stages. Each stage processes elements of a data stream, passing each processed data element to the next stage, and then taking on a new element before the subsequent stages have necessarily completed their processing. Pipeline parallelism is used especially in streaming applications that perform video, audio, and digital signal processing. Three out of 13 benchmarks in PARSEC, a popular software benchmark suite designed for shared-memory multiprocessors, can be expressed as pipeline parallelism. Whereas most concurrency platforms that support pipeline parallelism use a "construct-and-run" approach, this paper investigates "on-the-fly" pipeline parallelism, where the structure of the pipeline emerges as the program executes rather than being specified a priori. On-the-fly pipeline parallelism allows the number of stages to vary from iteration to iteration and dependencies to be data dependent. We propose simple linguistics for specifying on-the-fly pipeline parallelism and describe a provably efficient scheduling algorithm, the PIPER algorithm, which integrates pipeline parallelism into a work-stealing scheduler, allowing pipeline and fork-join parallelism to be arbitrarily nested. The PIPER algorithm automatically throttles the parallelism, precluding "runaway" pipelines. Given a pipeline computation with T1 work and T 00 span (critical-path length), PIPER executes the computation on P processors in Tp ≤ T1 /P+O(T∞ + Ig P) expected time. PIPER also limits stack space, ensuring that it does not grow unboundedly with running time. We have incorporated on-the-fly pipeline parallelism into a Cilkbased work-stealing runtime system. Our prototype Cilk-P implementation exploits optimizations such as lazy enabling and dependency folding. We have ported the three PARSEC benchmarks that exhibit pipeline parallelism to run on Cilk-P. One of these, x264, cannot readily be executed by systems that suppor

关键词： parallel programming

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Chimera grids for water simulation 13

Chimera grids for water simulation

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12th acm SIGGRAPH / Eurographics symposium on Computer Animation, SCA 2013

作者： Elliot English, R. Qiu, Linhai Yu, Yue Fedkiw, Ronald Stanford University United States Industrial Light + Magic United States

ISBN: (纸本)9781450321327

We introduce a new method for large scale water simulation using Chimera grid embedding, which discretizes space with overlapping Cartesian grids that translate and rotate in order to decompose the domain into different regions of interest with varying spatial resolutions. Grids can track both fluid features and solid objects, allowing for dynamic spatial adaptivity without remeshing or repartitioning the domain. We solve the inviscid incompressible Navier- Stokes equations with an arbitrary-Lagrangian-Eulerian style semi- Lagrangian advection scheme and a monolithic SPD Poisson solver. We modify the particle level set method in order to adapt it to Chimera grids including particle treatment across grid boundaries with disparate cell sizes, and strategies to deal with locality in the implementation of the level set and fast marching algorithms. We use a local Voronoi mesh construction to solve for pressure and address a number of issues that arise with the treatment of the velocity near the interface. The resulting method is highly scalable on distributed parallel architectures with minimal communication costs.

关键词： parallel architectures

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Empirical Evaluation of the parallel Distribution Sweeping Framework on Multicore architectures

Empirical Evaluation of the Parallel Distribution Sweeping F...

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21st annual European symposium on algorithms (ESA)

作者： Ajwani, Deepak Sitchinava, Nodari Bell Labs Ireland Dublin Ireland Karlsruhe Inst Technol D-76021 Karlsruhe Germany Univ Hawaii Honolulu HI 96822 USA

ISBN: (纸本)9783642404504

In this paper, we perform an empirical evaluation of the parallel External Memory (PEM) model in the context of geometric problems. In particular, we implement the parallel distribution sweeping framework of Ajwani, Sitchinava and Zeh to solve batched 1-dimensional stabbing max problem. While modern processors consist of sophisticated memory systems (multiple levels of caches, set associativity, TLB, prefetching), we empirically show that algorithms designed in simple models, that focus on minimizing the I/O transfers between shared memory and single level cache, can lead to efficient software on current multicore architectures. Our implementation exhibits significantly fewer accesses to slow DRAM and, therefore, outperforms traditional approaches based on plane sweep and two-way divide and conquer.

关键词： Dynamic random access storage

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Data Layout Optimization for GPGPU architectures 13

Data Layout Optimization for GPGPU Architectures

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18th acm SIGPLAN symposium on Principles and Practice of parallel Programming

作者： Liu, Jun Ding, Wei Jang, Ohyoung Kandemir, Mahmut Penn State Univ University Pk PA 16802 USA

ISBN: (纸本)9781450319225

GPUs are being widely used in accelerating general-purpose applications, leading to the emergence of GPGPU architectures. New programming models, e. g., Compute Unified Device Architecture (CUDA), have been proposed to facilitate programming general-purpose computations in GPGPUs. However, writing high-performance CUDA codes manually is still tedious and difficult. In particular, the organization of the data in the memory space can greatly affect the performance due to the unique features of a custom GPGPU memory hierarchy. In this work, we propose an automatic data layout transformation framework to solve the key issues associated with a GPGPU memory hierarchy (i.e., channel skewing, data coalescing, and bank conflicts). Our approach employs a widely applicable strategy based on a novel concept called data localization. Specifically, we try to optimize the layout of the arrays accessed in affine loop nests, for both the device memory and shared memory, at both coarse grain and fine grain parallelization levels. We performed an experimental evaluation of our data layout optimization strategy using 15 benchmarks on an NVIDIA CUDA GPU device. The results show that the proposed data transformation approach brings around 4.3X speedup on average.

关键词： algorithms Design Performance Experimentation GPGPU Data Layout Transformation CUDA Optimization

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Scheduling parallel Programs by Work Stealing with Private Deques 13

Scheduling Parallel Programs by Work Stealing with Private D...

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18th acm SIGPLAN symposium on Principles and Practice of parallel Programming

作者： Acar, Umut A. Chargueraud, Arthur Rainey, Mike Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA Univ Paris 11 CNRS LRI Orsay France

ISBN: (纸本)9781450319225

Work stealing has proven to be an effective method for scheduling parallel programs on multicore computers. To achieve high performance, work stealing distributes tasks between concurrent queues, called deques, which are assigned to each processor. Each processor operates on its deque locally except when performing load balancing via steals. Unfortunately, concurrent deques suffer from two limitations: 1) local deque operations require expensive memory fences in modern weak-memory architectures, 2) they can be very difficult to extend to support various optimizations and flexible forms of task distribution strategies needed many applications, e. g., those that do not fit nicely into the divide-and-conquer, nested data parallel paradigm. For these reasons, there has been a lot recent interest in implementations of work stealing with non-concurrent deques, where deques remain entirely private to each processor and load balancing is performed via message passing. Private deques eliminate the need for memory fences from local operations and enable the design and implementation of efficient techniques for reducing task-creation overheads and improving task distribution. These advantages, however, come at the cost of communication. It is not known whether work stealing with private deques enjoys the theoretical guarantees of concurrent deques and whether they can be effective in practice. In this paper, we propose two work-stealing algorithms with private deques and prove that the algorithms guarantee similar theoretical bounds as work stealing with concurrent deques. For the analysis, we use a probabilistic model and consider a new parameter, the branching depth of the computation. We present an implementation of the algorithm as a C++ library and show that it compares well to Cilk on a range of benchmarks. Since our approach relies on private deques, it enables implementing flexible task creation and distribution strategies. As a specific example, we show how to impleme

关键词： work stealing nested parallelism dynamic load balancing

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Locality-Aware Task Management for Unstructured parallelism: A Quantitative Limit Study

Locality-Aware Task Management for Unstructured Parallelism:...

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

作者： Yoo, Richard M. Hughes, Christopher J. Kim, Changkyu Chen, Yen-Kuang Kozyrakis, Christos Parallel Computing Laboratory Intel Labs Santa Clara CA 95054 United States Pervasive Parallelism Laboratory Stanford University Stanford CA 94305 United States

ISBN: (纸本)9781450315722

As we increase the number of cores on a processor die, the onchip cache hierarchies that support these cores are getting larger, deeper, and more complex. As a result, non-uniform memory access effects are now prevalent even on a single chip. To reduce execution time and energy consumption, data access locality should be exploited. This is especially important for task-based programming systems, where a scheduler decides when and where on the chip the code segments, i.e., tasks, should execute. Capturing locality for structured task parallelism has been done effectively, but the more difficult case, unstructured parallelism, remains largely unsolved-little quantitative analysis exists to demonstrate the potential of locality-aware scheduling, and to guide future scheduler implementations in the most fruitful direction. This paper quantifies the potential of locality-aware scheduling for unstructured parallelism on three different many-core processors. Our simulation results of 32-core systems show that localityaware scheduling can bring up to 2.39x speedup over a randomized schedule, and 2.05x speedup over a state-of-the-art baseline scheduling scheme. At the same time, a locality-aware schedule reduces average energy consumption by 55% and 47%, relative to the random and the baseline schedule, respectively. In addition, our 1024-core simulation results project that these benefits will only increase: Compared to 32-core executions, we see up to 1.83x additional locality benefits. To capture such potentials in a practical setting, we also perform a detailed scheduler design space exploration to quantify the impact of different scheduling decisions. We also highlight the importance of locality-aware stealing, and demonstrate that a stealing scheme can exploit significant locality while performing load balancing. Over randomized stealing, our proposed scheme shows up to 2.0x speedup for stolen tasks. Copyright is held by the owner/author(s). Publication rights licensed

关键词： Scheduling

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Executing dynamic data-graph computations deterministically using chromatic scheduling 14

Executing dynamic data-graph computations deterministically ...

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Proceedings of the 26th acm symposium on parallelism in algorithms and architectures

作者： Tim Kaler William Hasenplaugh Tao B. Schardl Charles E. Leiserson MIT CSAIL Cambridge MA USA

ISBN: (纸本)9781450328210

A data-graph computation — popularized by such programming systems as Galois, Pregel, GraphLab, PowerGraph, and GraphChi — is an algorithm that performs local updates on the vertices of a graph. During each round of a data-graph computation, an update function atomically modifies the data associated with a vertex as a function of the vertex's prior data and that of adjacent vertices. A dynamic data-graph computation updates only an active subset of the vertices during a round, and those updates determine the set of active vertices for the next *** paper introduces PRISM, a chromatic-scheduling algorithm for executing dynamic data-graph computations. PRISM uses a vertex-coloring of the graph to coordinate updates performed in a round, precluding the need for mutual-exclusion locks or other nondeterministic data synchronization. A multibag data structure is used by PRISM to maintain a dynamic set of active vertices as an unordered set partitioned by color. We analyze PRISM using work-span analysis. Let G=(V,E) be a degree-Δ graph colored with Χ colors, and suppose that Q⊆V is the set of active vertices in a round. Define size(Q)=[Q] + Σv∈Qdeg(v), which is proportional to the space required to store the vertices of Q using a sparse-graph layout. We show that a P-processor execution of PRISM performs updates in Q using O(Χ(lg (Q/Χ)+lgΔ)+ lgP) span and Θ(size(Q)+Χ+P) work. These theoretical guarantees are matched by good empirical performance. We modified GraphLab to incorporate PRISM and studied seven application benchmarks on a 12-core multicore machine. PRISM executes the benchmarks 1.2–2.1 times faster than GraphLab's nondeterministic lock-based scheduler while providing deterministic *** paper also presents PRISM-R, a variation of PRISM that executes dynamic data-graph computations deterministically even when updates modify global variables with associative operations. PRISM-R satisfies the same theoretical bounds as PRISM, but its implementation is

关键词： determinism reducers multithreading parallel programming work stealing data-graph computations chromatic scheduling multicore

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