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WeeFence: Toward making fences free in TSO 13

WeeFence: Toward making fences free in TSO

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40th annual International symposium on Computer Architecture, ISCA 2013

作者： Duan, Yuelu Muzahid, Abdullah Torrellas, Josep University of Illinois Urbana-Champaign United States University of Texas San Antonio United States

ISBN: (纸本)9781450320795

Although fences are designed for low-overhead concurrency coordination, they can be expensive in current machines. If fences were largely free, faster fine-grained concurrent algorithms could be devised, and compilers could guarantee Sequential Consistency (SC) at little cost. In this paper, we present WeeFence (or WFence for short), a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only when an incorrect reordering of accesses is about to happen, does the hardware stall to prevent it. In the paper, we present the WFence design for TSO, and compare it to a conventional fence with speculation for 8-processor multicore simulations. We run parallel kernels that contain explicit fences and parallel applications that do not. For the kernels, WFence eliminates nearly all of the fence stall, reducing the kernels' execution time by an average of 11%. For the applications, a conservative compiler algorithm places fences in the code to guarantee SC. In this case, on average, WFences reduce the resulting fence overhead from 38% of the applications' execution time to 2% (in a centralized WFence design), or from 36% to 5% (in a distributed WFence design). Copyright 2013 acm.

关键词： parallel programming

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Distributed algorithms for barrier coverage using relocatable sensors 13

Distributed algorithms for barrier coverage using relocatabl...

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2013 acm symposium on Principles of Distributed Computing, PODC 2013

作者： Eftekhari, Mohsen Kranakis, Evangelos Krizanc, Danny Morales-Ponce, Oscar Narayanan, Lata Opatrny, Jaroslav Dept. Comp. Sci. and Soft. Eng. Concordia University Montreal Canada School of Comp. Sci. Carleton University Ottawa Canada Dept. of Math. and Comp. Sci. Wesleyan University Middletown United States Dept. of Comp. Science Chalmers U. of Tech. Gothenburg Sweden

ISBN: (纸本)9781450320658

We study the barrier coverage problem using relocatable sensor nodes. We assume each sensor can sense an intruder or event inside its sensing range. Sensors are initially located at arbitrary positions on the barrier and can move along the barrier. The goal is to find final positions for sensors so that the entire barrier is covered. In recent years, the problem has been studied extensively in the centralized setting. In this paper, we study the problem in the distributed setting. We assume each sensor repeatedly executes a Look-Compute-Move cycle: based on what it sees in its vicinity, it makes a decision on where to move, and moves to its next position. We make two strong but realistic restrictions on the capabilities of sensors: they have a constant visibility rang e and can move only a constant distance in every cycle. In this model, we give the first two distributed algorithms that achieve barrier coverage for a line segment barrier when there are enough nodes in the network to cover the entire barrier. Our algorithms are synchronous, and local in the sense that sensors make their decisions independently based only on what they see within their constant visibility range. One of our algorithms is oblivious whereas the other uses two bits of memory at each sensor to store the type of move made in the previous step. We show that our oblivious algorithm terminates within θ(n2) steps with the barrier fully covered, while the constant-memory algorithm is shown to take θ(n) steps to terminate in the worst case. Since any algorithm that can only move a constant distance in one step requires ω(n) steps on some inputs, our second algorithm is asymptotically optimal. Finally, both our algorithms are self-stabilizing, and can be easily extended to the case of non-homogeneous sensors, and for the case when the barrier is a circle. Copyright 2013 acm.

关键词： parallel algorithms

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Cross-Architectural study of custom reconfigurable devices using crowdsourcing

Cross-Architectural study of custom reconfigurable devices u...

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2013 IEEE 37th annual Computer Software and Applications Conference, COMPSAC 2013

作者： Sistla, Anilkumar Parde, Natalie Patel, Krunalkumar Mehta, Gayatri University of North Texas Denton TX 76207 United States

ISBN: (纸本)9780769549798

Coarse grained reconfigurable architectures (CGRAs) are promising due to the ability to highly customize such architectures to an application domain. However, good tools and good algorithms to map benchmarks onto these architectures are needed to support design space exploration for CGRAs. In particular, the mapping problem has been difficult to solve in a satisfying and general way. In this paper, we present an architectural design flow using crowd sourcing to provide mappings of benchmarks onto new architectures. We show that the crowd can provide high quality, reliable mappings, outperforming our custom Simulated Annealing algorithm in 37 of 42 trials. We further show that the crowd can provide other types of feedback that are difficult to obtain from an automatic mapping algorithm. Our proof of concept cross-Architectural study concludes that a mesh architecture with 8Way connectivity outperforms the other interconnection options tested. A stripe architecture with dedicated vertical routes (StripeDR) performs competitively as well. © 2013 IEEE.

关键词： Reconfigurable architectures

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Designing Optimized MPI Broadcast and Allreduce for Many Integrated Core (MIC) InfiniBand Clusters

Designing Optimized MPI Broadcast and Allreduce for Many Int...

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21st annual IEEE symposium on High-Performance Interconnects (HOTI)

作者： Kandalla, K. Venkatesh, A. Hamidouche, K. Potluri, S. Bureddy, D. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9780769551036

The emergence of co-processors such as Intel Many Integrated Cores (MICs) is changing the landscape of supercomputing. The MIC is a memory constrained environment and its processors also operate at slower clock rates. Furthermore, the communication characteristics between MIC processes are also different compared to communication between host processes. Communication libraries that do not consider these architectural subtleties cannot deliver good communication performance. The performance of MPI collective operations strongly affect the performance of parallel applications. Owing to the challenges introduced by the emerging heterogeneous systems, it is critical to fundamentally re-design collective algorithms to ensure that applications can fully leverage the MIC architecture. In this paper, we propose a generic framework to optimize the performance of important collective operations, such as, MPI_Bcast, MPI_Reduce and MPI_Allreduce, on Intel MIC clusters. We also present a detailed analysis of the compute phases in reduce operations for MIC clusters. To the best of our knowledge, this is the first paper to propose novel designs to improve the performance of collectives on MIC clusters. Our designs improve the latency of the MPI_Bcast operation with 4,864 MPI processes by up to 76%. We also observe up to 52.4% improvements in the communication latency of the MPI_Allreduce operation with 2K MPI processes on heterogeneous MIC clusters. Our designs also improve the execution time of the WindJammer application by up to 16%.

关键词： application program interfaces clocks coprocessors message passing multiprocessing systems parallel architectures performance evaluation

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Designing hybrid architectures for massive-scale graph analysis

Designing hybrid architectures for massive-scale graph analy...

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2013 IEEE 37th annual Computer Software and Applications Conference, COMPSAC 2013

作者： Ediger, David Bader, David A. Georgia Institute of Technology United States

ISBN: (纸本)9780769549798

Turning large volumes of data into actionable knowledge is a top challenge in high performance computing. Our previous work in this area demonstrated algorithmic techniques for massively parallel graph analysis on multithreaded systems. This work led to the development of GraphCT, the first end-to-end graph analytics platform for the Cray XMT and x86-class systems with OpenMP, and STINGER, a high performance, multithreaded, dynamic graph data structure and algorithms. Both of these packages are freely available as open source software. This dissertation research culminates in experimental and analytical techniques to study the marriage of disk-based systems, such as Hadoop, with shared memory-based systems, such as the Cray XMT, for data-intensive applications. David Ediger is a fifth year PhD candidate in Electrical and Computer Engineering. © 2013 IEEE.

关键词： Open source software

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Accelerating all-to-All protein structures comparison with tmalign using a noc many-cores processor architecture

Accelerating all-to-All protein structures comparison with t...

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2013 IEEE 37th annual Computer Software and Applications Conference, COMPSAC 2013

作者： Sharma, Anuj Papanikolaou, Antonis Manolakos, Elias S. Department of Informatics and Telecommunications University of Athens Athens Greece Institute of Communication and Computer Systems National Technical University Athens Greece

ISBN: (纸本)9780769549798

Computational challenges for the one-to-many and many-to-many protein structure comparison (PSC) problem are a result of several factors: constantly expanding large-size structural proteomics databases, high computational complexity of pair wise protein comparison algorithms, and the multitude of pair wise comparison approaches used in the field. Advances in processor architectures, such as manycore CPUs, have enabled them to support parallelism making them of interest in speeding up PSC techniques. We presentrckAlign, an implementation of the popularly used TM-AlignPSC algorithm, designed for the Single-Chip Cloud Computer(SCC), an experimental processor created by Intel Labs. We developed a skeleton library, rckskel, and implemented amaster-slaves variant of TM-Align to exploit the parallelism offered by the SCC. We evaluated rckAlign on the SCC and compared it with existing TM-Align software running on a dualcore AMD CPU (2.4 GHz) and on a single-core Intel P54CPentium CPU (800 MHz). We observed an 11-fold speedup relatively to the former and a 44-fold speedup relatively to the latter. A key aspect of the performance of rckAlign on the SCC, is the almost linear speedup achieved with the number of SCC cores used as slaves. The method presented can easily be applied to other PSC algorithms and extended to running multiple PSC algorithms within the same SCC chip. © 2013 IEEE.

关键词： parallel algorithms

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Locality-Aware Task Management for Unstructured parallelism: A Quantitative Limit Study 13

Locality-Aware Task Management for Unstructured Parallelism:...

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annual acm symposium on parallel algorithms and architectures

作者： Richard M. Yoo Christopher J. Hughes Changkyu Kim Yen-Kuang Chen Christos Kozyrakis Parallel Computing Laboratory Intel Labs Santa Clara CA 95054 Pervasive Parallelism Laboratory Stanford University Stanford CA 94305

ISBN: (纸本)9781450315722

As we increase the number of cores on a processor die, the on-chip cache hierarchies that support these cores are getting larger, deeper, and more complex. As a result, non-uniform memory access effects are now prevalent even on a single chip. To reduce execution time and energy consumption, data access locality should be exploited. This is especially important for task-based programming systems, where a scheduler decides when and where on the chip the code segments, i.e., tasks, should execute. Capturing locality for structured task parallelism has been done effectively, but the more difficult case, unstructured parallelism, remains largely unsolved-little quantitative analysis exists to demonstrate the potential of locality-aware scheduling, and to guide future scheduler implementations in the most fruitful direction. This paper quantifies the potential of locality-aware scheduling for unstructured parallelism on three different many-core processors. Our simulation results of 32-core systems show that locality-aware scheduling can bring up to 2.39x speedup over a randomized schedule, and 2.05x speedup over a state-of-the-art baseline scheduling scheme. At the same time, a locality-aware schedule reduces average energy consumption by 55% and 47%, relative to the random and the baseline schedule, respectively. In addition, our 1024-core simulation results project that these benefits will only increase: Compared to 32-core executions, we see up to 1.83x additional locality benefits. To capture such potentials in a practical setting, we also perform a detailed scheduler design space exploration to quantify the impact of different scheduling decisions. We also highlight the importance of locality-aware stealing, and demonstrate that a stealing scheme can exploit significant locality while performing load balancing. Over randomized stealing, our proposed scheme shows up to 2.0x speedup for stolen tasks.

关键词： Task Scheduling Task Stealing Locality Performance Energy

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Truly parallel burrows-wheeler compression and decompression 13

Truly parallel burrows-wheeler compression and decompression

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Proceedings of the twenty-fifth annual acm symposium on parallelism in algorithms and architectures

作者： James Alexander Edwards Uzi Vishkin University of Maryland College Park USA

ISBN: (纸本)9781450315722

We present novel work-optimal PRAM algorithms for Burrows-Wheeler (BW) compression and decompression of strings over a constant alphabet. For a string of length n, the depth of the compression algorithm is O(log2 n), and the depth of the corresponding decompression algorithm is O(log n). These appear to be the first polylogarithmic-time work-optimal parallel algorithms for any standard lossless compression *** algorithms for the individual stages of compression and decompression may also be of independent interest: 1. a novel O(log n)-time, O(n)-work PRAM algorithm for Huffman decoding; 2. original insights into the stages of the BW compression and decompression problems, bringing out parallelism that was not readily apparent. We then mapped such parallelism in interesting ways to elementary parallel routines that have O(log n)-time, O(n)-work solutions, such as: (i) prefix-sums problems with an appropriately-defined associative binary operator for several stages, and (ii) list ranking for the final stage of decompression (inverse blocksorting transform).Companion work reports empirical speedups of up to 25x for compression and up to 13x for decompression. This reflects a speedup of 70x over recent work on BW compression on GPUs.

关键词： burrows-wheeler lossless compression parallel pram

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Hidp: A hierarchical data parallel language

Hidp: A hierarchical data parallel language

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International symposium on Code Generation and Optimization (CGO)

作者： Yongpeng Zhang Frank Mueller North Carolina State University Raleigh NC USA

ISBN: (纸本)9781467355247

Problem domains are commonly decomposed hierarchically to fully utilize parallel resources in modern microprocessors. Such decompositions can be provided as library routines, written by experienced experts, for general algorithmic patterns. But such APIs tend to be constrained to certain architectures or data sizes. Integrating them with application code is often an unnecessarily daunting task, especially when these routines need to be closely coupled with user code to achieve better performance. This paper contributes HiDP, a high-level hierarchical data parallel language. The purpose of HiDP is to improve the coding productivity of integrating hierarchical data parallelism without significant loss of performance. HiDP is a source-to-source compiler that converts a very concise data parallel language into CUDA C++ source code. Internally, it performs necessary analysis to compose user code with efficient and architecture-aware code snippets. This paper discusses various aspects of HiDP systematically: the language, the compiler and the run-time system with built-in tuning capabilities. They enable HiDP users to express algorithms in less code than low-level SDKs require for native platforms. HiDP also exposes abundant computing resources of modern parallel architectures. Improved coding productivity tends to come with a sacrifice in performance. Yet, experimental results show that the generated code delivers performance very close to handcrafted native GPU code.

关键词： Shape parallel processing Graphics processing units Arrays Kernel Synchronization Libraries

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Convergence and scalarization for data-parallel architectures

Convergence and scalarization for data-parallel architecture...

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International symposium on Code Generation and Optimization (CGO)

作者： Yunsup Lee Ronny Krashinsky Vinod Grover Stephen W. Keckler Krste Asanović University of California at Berkeley USA NVIDIA USA University of Texas at Austin USA

ISBN: (纸本)9781467355247

Modern throughput processors such as GPUs achieve high performance and efficiency by exploiting data parallelism in application kernels expressed as threaded code. One draw-back of this approach compared to conventional vector architectures is redundant execution of instructions that are common across multiple threads, resulting in energy inefficiency due to excess instruction dispatch, register file accesses, and memory operations. This paper proposes to alleviate these overheads while retaining the threaded programming model by automatically detecting the scalar operations and factoring them out of the parallel code. We have developed a scalarizing compiler that employs convergence and variance analyses to statically identify values and instructions that are invariant across multiple threads. Our compiler algorithms are effective at identifying convergent execution even in programs with arbitrary control flow, identifying two-thirds of the opportunity captured by a dynamic oracle. The compile-time analysis leads to a reduction in instructions dispatched by 29%, register file reads and writes by 31% memory address counts by 47%, and data access counts by 38%.

关键词： Instruction sets Convergence Registers Kernel Computer architecture Graphics processing units Algorithm design and analysis

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