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A parallel Tiled Solver for Dense Symmetric Indefinite Systems on Multicore architectures

A Parallel Tiled Solver for Dense Symmetric Indefinite Syste...

26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Baboulin, Marc Becker, Dulceneia Dongarra, Jack Inria Saclay Ile de France F-91893 Orsay France Univ Paris Sud F-91405 Orsay France Univ Tennessee Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester Lancs England

ISBN: (纸本)9780769546759

We describe an efficient and innovative parallel tiled algorithm for solving symmetric indefinite systems on multicore architectures. This solver avoids pivoting by using a multiplicative preconditioning based on symmetric randomization. This randomization prevents the communication overhead due to pivoting, is computationally inexpensive and requires very little storage. Following randomization, a tiled factorization is used that reduces synchronization by using static or dynamic scheduling. We compare Gflop/s performance of our solver with other types of factorizations on a current multicore machine and we provide tests on accuracy using LAPACK test cases.

关键词： dense linear algebra symmetric indefinite systems randomized algorithms tiled factorization

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Brief announcement: All-to-all gradecast using coding with byzantine failures 12

Brief announcement: All-to-all gradecast using coding with b...

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2012 acm symposium on Principles of Distributed Computing, PODC'12

作者： Bridgman III, John F. Garg, Vijay K. Parallel and Distributed Systems Lab. Electrical and Computer Engineering University of Texas at Austin Austin TX United States

No abstract available.

ISBN: (纸本)9781450314503

No abstract available.

关键词： fault tolerance broadcast distributed algorithms

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A parallel Resampling Algorithm for Particle Filtering on Shared-Memory architectures

A Parallel Resampling Algorithm for Particle Filtering on Sh...

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Gong, Peng Basciftci, Yuksel Ozan Ozguner, Fusun Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA

ISBN: (纸本)9780769546766

Many real-world applications such as positioning, navigation, and target tracking for autonomous vehicles require the estimation of some time-varying states based on noisy measurements made on the system. Particle filters can be used when the system model and the measurement model are not Gaussian or linear. However, the computational complexity of particle filters prevents them from being widely adopted. parallel implementation will make particle filters more feasible for real-time applications. Effective resampling algorithms like the systematic resampling algorithm are serial. In this paper, we propose the shared-memory systematic resampling (SMSR) algorithm that is easily parallelizable on existing architectures. We verify the performance of SMSR on graphics processing units. Experimental results show that the proposed SMSR algorithm can achieve a significant speedup over the serial particle filter.

关键词： particle filters resampling algorithm shared-memory architecture parallel computing

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Scalable Multi-threaded Community Detection in Social Networks

Scalable Multi-threaded Community Detection in Social Networ...

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Riedy, Jason Bader, David A. Meyerhenke, Henning Georgia Inst Technol Coll Comp Atlanta GA 30332 USA Karlsruhe Inst Technol Inst Theoret Informat Karlsruhe Germany

ISBN: (纸本)9780769546766

The volume of existing graph-structured data requires improved parallel tools and algorithms. Finding communities, smaller subgraphs densely connected within the subgraph than to the rest of the graph, plays a role both in developing new parallel algorithms as well as opening smaller portions of the data to current analysis tools. We improve performance of our parallel community detection algorithm by 20% on the massively multithreaded Cray XMT, evaluate its performance on the next-generation Cray XMT2, and extend its reach to Intel-based platforms with OpenMP. To our knowledge, not only is this the first massively parallel community detection algorithm but also the only such algorithm that achieves excellent performance and good parallel scalability across all these platforms. Our implementation analyzes a moderate sized graph with 105 million vertices and 3.3 billion edges in around 500 seconds on a four processor, 80-logical-core Intel-based system and 1100 seconds on a 64-processor Cray XMT2.

关键词： Detection algorithms Social Networks Scalability Platform parallel Lines Social Capital TRANSMITTING

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A new data reduction approach over the stream processor architecture

A new data reduction approach over the stream processor arch...

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26th IEEE International parallel and Distributed Processing symposium (IPDPS)

作者： Chen, Qingkui Xiao, Li Zhuang, Songlin Shanghai Univ Sci & Technol Sch Opt Elect & Comp Engn Shanghai 201800 Peoples R China

ISBN: (纸本)9780769546766

In order to solve the parallel processing problem of mass data, stream processor develops quickly in recent years. The essence of stream processor is getting high performance according to executing thousands of threads parallelly. It is widely used in scientific computing, data mining, video quality analysis and other fields. But mass threads means the high costs of thread synchronization. Mass computing time is wasted in the reduction of thread data. This paper provides a binary reduction algorithm based on three basic reduction algorithms according to CUDA parallel computing model. Experiments show that the performance of binary reduction algorithm is better than three basic reduction algorithms and it has great scalability.

关键词： A new data reduction approach stream processor architecture THREADS Processor architectures big data Mass data changes PROCESSOR data reduction streams parallel PROCESSING (COMPUTERS) Program Thread HIGH-PERFORMANCE new data

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Tight Bounds for Monotone Switching Networks via Fourier Analysis 12

Tight Bounds for Monotone Switching Networks via Fourier Ana...

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44th acm annual symposium on Theory of Computing (STOC)

作者： Chan, Siu Man Potechin, Aaron Univ Calif Berkeley Berkeley CA 94720 USA MIT Cambridge MA USA

ISBN: (纸本)9781450312455

We prove tight size bounds on monotone switching networks for the k-clique problem, and for an explicit monotone problem by analyzing the generation problem with a pyramid structure of height h. This gives alternative proofs of the separations of m-NC from m-P and of m-NCi from m-NCi+1, different from Raz-McKenzie (Combinatorica '99). The enumerative-combinatorial and Fourier analytic techniques in this work are very different from a large body of work on circuit depth lower bounds, and may be of independent interest.

关键词： Lower bounds space complexity parallel complexity monotone complexity switching networks

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Energy-aware scheduling: models and complexity results

Energy-aware scheduling: models and complexity results

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Aupy, Guillaume Ecole Normale Super Lyon LIP F-69364 Lyon 07 France

ISBN: (纸本)9780769546766

This paper presents several energy-aware scheduling algorithms whose design is optimized for different speed models. Dynamic Voltage and Frequency Scaling (DVFS) is a model frequently used to reduce the energy consumption of a schedule, but it has negative effect on reliability. While the reliability of a schedule can sometimes be neglected (battery powered systems such as cell-phones or personal computers), it becomes extremely important when considering massively parallel architectures (petascale, exascale). In this work, we consider the problem of minimizing the energy within a makespan constraint. Additionally, we consider two models, one that takes into account a reliability constraint, and one that does not. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. To improve the reliability of a schedule while reducing the energy consumption, we allow for the re-execution of some tasks. We present several results in that framework, as well as future research plans.

关键词： energy consumption Variable speed ordered list Religious Missions execution time parallel architectures BACKFILL PROCESSOR

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Vector Extensions for Decision Support DBMS Acceleration 45

Vector Extensions for Decision Support DBMS Acceleration

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45th IEEE/acm annual International symposium on Microarchitecture (MICRO)

作者： Hayes, Timothy Palomar, Oscar Unsal, Osman Cristal, Adrian Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9780769549248;9781467348195

Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has become an important area of investigation. This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using vector ISA extensions. In the first step, a leading DSS DBMS is analysed for potential data-level parallelism. We discuss why the existing multimedia SIMD extensions (SSE/AVX) are not suitable for capturing this parallelism and propose a complementary instruction set reminiscent of classical vector architectures. The instruction set is implemented using unintrusive modifications to a modern x86-64 microarchitecture tailored for DSS DBMS. The ISA and microarchitecture are evaluated using a cycle-accurate x86-64 microarchitectural simulator coupled with a highly-detailed memory simulator. We have found a single operator is responsible for 41% of total execution time for the TPC-H DSS benchmark. Our results show performance speedups between 1.94x and 4.56x for an implementation of this operator run with our proposed hardware modifications.

关键词： computer centres database management systems decision support systems instruction sets memory architecture microprocessor chips parallel architectures

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Comparison of GPU architectures for asynchronous communication with finite-differencing applications

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2012年第1期24卷 73-83页

作者： Playne, D. P. Hawick, K. A. Massey Univ Inst Informat & Math Sci Auckland New Zealand

Graphical processing units (GPUs) are good data-parallel performance accelerators for solving regular mesh partial differential equations (PDEs) whereby low-latency communications and high compute to communications ratios can yield very high levels of computational efficiency. Finite-difference time-domain methods still play an important role for many PDE applications. Iterative multi-grid and multilevel algorithms can converge faster than ordinary finite-difference methods but can be much more difficult to parallelize with GPU memory constraints. We report on some practical algorithmic and data layout approaches and on performance data on a range of GPUs with CUDA. We focus on the use of multiple GPU devices with a single CPU host and the asynchronous CPU/GPU communications issues involved. We obtain more than two orders of magnitude of speedup over a comparable CPU core. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： finite-difference GPU multiple device CUDA

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Merge Path - parallel Merging Made Simple

Merge Path - Parallel Merging Made Simple

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Odeh, Saher Green, Oded Mwassi, Zahi Shmueli, Oz Birk, Yitzhak Technion Israel Inst Technol Dept Elect Engn IL-32000 Haifa Israel

ISBN: (纸本)9780769546766

Merging two sorted arrays is a prominent building block for sorting and other functions. Its efficient parallelization requires balancing the load among compute cores, minimizing the extra work brought about by parallelization, and minimizing inter-thread synchronization requirements. Efficient use of memory is also important. We present a novel approach to partitioning the two sorted arrays into pairs of contiguous sequences of elements, one from each array, such that 1) each pair comprises any desired total number of elements, and 2) the elements of each pair form a contiguous sequence in the final merged sorted array. While the resulting partition and the computational complexity are similar to those of certain previous algorithms, our approach is different, extremely intuitive, and offers interesting insights. Based on this, we present a synchronization-free, cache-efficient merging (and sorting) algorithm. While we use CREW PRAM as the basis, our algorithm is easily adaptable to additional architectures. In fact, our approach is even relevant to sequential cache-efficient sorting. The algorithms and performance results are presented, along with important cache-related insights.

关键词： component parallelism and concurrency parallel processors Sorting and searching

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