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DAG3: A tool for design and analysis of applications for multicore architectures 12

DAG3: A tool for design and analysis of applications for mul...

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27th annual acm symposium on Applied Computing, SAC 2012

作者： Drago, Mauro Luigi Bishop, Judith Politecnico di Milano - DEI Piazza L. Da Vinci 32 20133 Milano Italy Microsoft Research One Microsoft Way Redmond WA 98033 United States

ISBN: (纸本)9781450308571

Despite the availability of libraries and constructs in modern programming languages to support the development of parallel applications, achieving the desired performance improvement can still be difficult. Design patterns and idioms simplify writing of applications but, if they are not applied correctly, the introduced overhead may overwhelm the benefits of parallelism. Performance and parallelism deserve specific software engineering techniques in order to be successfully accounted. In this sense, software design and performance analysis techniques represent a valid option to discover problems in the early stages of development and manage them in an structured manner. In this paper we present Dag3: a tool and a methodology leveraging Direct Acyclic Graphs to design parallel applications and to analyze their performance. parallel applications are designed by specifying the constituents of the computation, their organization, and their contribution to performance. Parametric analyses can be conducted to estimate performance metrics, such as speedup, and to the identify the critical parts of a computation. To increase programmers' productivity, models can be also used to generate part of the application source code. © 2012 acm.

关键词： Software design

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ShyLU: A Hybrid-Hybrid Solver for Multicore Platforms

ShyLU: A Hybrid-Hybrid Solver for Multicore Platforms

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Rajamanickam, Sivasankaran Boman, Erik G. Heroux, Michael A. Sandia Natl Labs Livermore CA 94550 USA

ISBN: (纸本)9780769546759

With the ubiquity of multicore processors, it is crucial that solvers adapt to the hierarchical structure of modern architectures. We present ShyLU, a "hybrid-hybrid" solver for general sparse linear systems that is hybrid in two ways: First, it combines direct and iterative methods. The iterative part is based on approximate Schur complements where we compute the approximate Schur complement using a value-based dropping strategy or structure-based probing strategy. Second, the solver uses two levels of parallelism via hybrid programming (MPI+threads). ShyLU is useful both in shared-memory environments and on large parallel computers with distributed memory. In the latter case, it should be used as a subdomain solver. We argue that with the increasing complexity of compute nodes, it is important to exploit multiple levels of parallelism even within a single compute node. We show the robustness of ShyLU against other algebraic preconditioners. ShyLU scales well up to 384 cores for a given problem size. We also study the MPI-only performance of ShyLU against a hybrid implementation and conclude that on present multicore nodes MPI-only implementation is better. However, for future multicore machines (96 or more cores) hybrid/hierarchical algorithms and implementations are important for sustained performance.

关键词： Solvers Multi-core processors modern architectures parallelism distributed memory HYBRID hierarchical structure instruction-level parallelism Synclitism

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GPUs as an Opportunity for Offloading Garbage Collection 12

GPUs as an Opportunity for Offloading Garbage Collection

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2012 International symposium on Memory Management

作者： Maas, Martin Reames, Philip Morlan, Jeffrey Asanovic, Krste Joseph, Anthony D. Kubiatowicz, John Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450313506

GPUs have become part of most commodity systems. Nonetheless, they are often underutilized when not executing graphics-intensive or special-purpose numerical computations, which are rare in consumer workloads. Emerging architectures, such as integrated CPU/GPU combinations, may create an opportunity to utilize these otherwise unused cycles for offloading traditional systems tasks. Garbage collection appears to be a particularly promising candidate for offloading, due to the popularity of managed languages on consumer devices. We investigate the challenges for offloading garbage collection to a GPU, by examining the performance trade-offs for the mark phase of a mark & sweep garbage collector. We present a theoretical analysis and an algorithm that demonstrates the feasibility of this approach. We also discuss a number of algorithmic design trade-offs required to leverage the strengths and capabilities of the GPU hardware. Our algorithm has been integrated into the Jikes RVM and we present promising performance results.

关键词： Design Experimentation Languages Performance algorithms parallel garbage collection mark and sweep SIMT GPU APU

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On the Feasibility of a Distributed Runtime for the Chemical Programming Model

On the Feasibility of a Distributed Runtime for the Chemical...

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26th IEEE International parallel and Distributed Processing symposium (IPDPS)

作者： Obrovac, Marko Tedeschi, Cedric Univ Rennes 1 INRIA IRISA F-35014 Rennes France

ISBN: (纸本)9780769546766

Chemical computing was initially proposed as an intuitive paradigm to capture the essence of parallel computing. Within such a model, a program is a solution of information-carrying molecules, that, at run time, collide non-deterministically to produce new data. Such a paradigm allowed the programmers to focus on the logic of the problem to be solved in parallel, without having to worry about implementation's considerations. Throughout the years, the model has been enriched with various features related to program structure, control and practicability. More importantly, the model was raised to the higher order, increasing again its expressiveness. With the rise of service-oriented computing, such models have recently regained a lot of interest. They have been shown to provide adequate abstractions to enhance service-oriented architectures with autonomic properties such as self-adaptation, self-healing, or self-organisation. However, the deployment of chemical programs over large scale distributed platforms is still a widely open problem, hindering the model to be leveraged in practice. This paper studies the possibility of building a distributed execution environment for chemical programs. A generic peer-to-peer-based runtime model and distributed algorithms for large scale chemical computing are discussed. To complete this study, a software prototype was developed and experimented over the Grid'5000 test-bed. Experimental performance results are detailed, allowing for a discussion of the feasibility and performance of such a runtime, thus lifting a barrier towards the enactment of the chemical programming model.

关键词： Runtime Software prototyping chemical compounds Service-oriented architecture distributed algorithms Computer personnel Programming parallel PROCESSING (COMPUTERS) Worry Distribute Essences Formal logic

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A Highly parallel Reuse Distance Analysis Algorithm on GPUs

A Highly Parallel Reuse Distance Analysis Algorithm on GPUs

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26th IEEE International parallel and Distributed Processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Cui, Huimin Yi, Qing Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Chinese Acad Sci SKL Comp Architecture Inst Comp Technol Beijing Peoples R China Univ Texas CAS Dept Comp Sci San Antonio TX USA Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9780769546759

Reuse distance analysis is a runtime approach that has been widely used to accurately model the memory system behavior of applications. However, traditional reuse distance analysis algorithms use tree-based data structures and are hard to parallelize, missing the tremendous computing power of modern architectures such as the emerging GPUs. This paper presents a highly-parallel reuse distance analysis algorithm (HP-RDA) to speedup the process using the SPMD execution model of GPUs. In particular, we propose a hybrid data structure of hash table and local arrays to flatten the traditional tree representation of memory access traces. Further, we use a probabilistic model to correct any loss of precision from a straightforward parallelization of the original sequential algorithm. Our experimental results show that using an NVIDIA GPU, our algorithm achieves a factor of 20 speedup over the traditional sequential algorithm with less than 1% loss in precision.

关键词： Reuse reuse modern architectures Data structures sequential algorithm Hash table Precision Probabilistic Model Runtime Speeding algorithms

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Or-parallel Prolog execution on multicores based on stack splitting

Or-parallel Prolog execution on multicores based on stack sp...

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7th Workshop on Declarative Aspects and Applications of Multicore Programming, DAMP'12, Co-located with POPL 2012

作者： Vieira, Rui Rocha, Ricardo Silva, Fernando CRACS and INESC TEC Faculty of Sciences University of Porto Rua do Campo Alegre 1021/1055 4169-007 Porto Portugal

ISBN: (纸本)9781450311175

Many or-parallel Prolog computational models exploiting implicit parallelism have been proposed in the past. The Muse and YapOr systems are arguably two of the most efficient systems exploiting or-parallelism on shared memory architectures, both based on the environment copying model. Stack splitting emerged as an alternative model specially geared to distributed memory architectures as it basically splits the computation in such a way that no further, or just minimal, synchronization is required. With the new multicore architectures, it just makes sense to recover the body of knowledge there is in this area and reengineer prior computational models to evaluate their performance on newer architectures. In this paper, we focus on the design and implementation of stack splitting in the YapOr system. Our aim is to take advantage of its robustness to efficiently implement stack splitting support using shared memory, and then be able to directly compare the original YapOr with the YapOr using stack splitting. We consider two splitting models, vertical splitting and half splitting, and have adapted data structures, scheduling and incremental copy procedures in YapOr to cope with the new models. Experimental results, on a multicore machine with 24 cores, show that YapOr using stack splitting is, in general, comparable to the original YapOr, obtaining in some cases better performance than with only environment copying. Copyright © 2012 acm.

关键词： Logic programming

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In Search of parallel Dimensions 12

In Search of Parallel Dimensions

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annual acm symposium on parallel algorithms and architectures

作者： Ravi Rajwar Intel Corporation

ISBN: (纸本)9781450312134

Performance matters. But how we improve it is changing. Historically, transparent hardware improvements would mean software just ran faster. That may not necessarily be true in the future. To continue the pace of innovation, the future will need to be increasingly parallel- involving parallelism across data, threads, cores, and nodes. This talk will explore some of the dimensions of parallelism, and the opportunities and challenges they pose.

关键词： parallelism Performance Synchronization Vectors Concurrency Synclitism parallelism Concurrency dimensions Cloning Vectors core

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When the Cut Condition is Enough: A Complete Characterization for Multiflow Problems in Series-parallel Networks 12

When the Cut Condition is Enough: A Complete Characterizatio...

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44th acm annual symposium on Theory of Computing (STOC)

作者： Chakrabarti, Amit Fleischer, Lisa Weibel, Christophe Dartmouth Coll Comp Sci Hanover NH 03755 USA Google Inc Mountain View CA USA

ISBN: (纸本)9781450312455

Let G = (V, E) be a supply graph and H = (V, F) a demand graph defined on the same set of vertices. An assignment of capacities to the edges of G and demands to the edges of H is said to satisfy the cut condition if for any cut in the graph, the total demand crossing the cut is no more than the total capacity crossing it. The pair (G, H) is called cut-sufficient if for any assignment of capacities and demands that satisfy the cut condition, there is a multiflow routing the demands defined on H within the network with capacities defined on G. We prove a previous conjecture, which states that when the supply graph G is series -parallel, the pair (G, H) is cut-sufficient if and only if (G, H) does not contain an odd spindle as a minor;that is, if it is impossible to contract edges of G and delete edges of G and H so that G becomes the complete bipartite graph K2,p, with p > 3 odd, and H is composed of a cycle connecting the p vertices of degree 2, and an edge connecting the two vertices of degree p. We further prove that if the instance is Eulerian that is, the demands and capacities are integers and the total of demands and capacities incident to each vertex is even then the multiflow problem has an integral solution. We provide a polynomial -time algorithm to find an integral solution in this case. In order to prove these results, we formulate properties of tight cuts (cuts for which the cut condition inequality is tight) in cutsufficient pairs. We believe these properties might be useful in extending our results to planar graphs.

关键词： Network flows Series-parallel graphs

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Can Traditional Programming Bridge the Ninja Performance Gap for parallel Computing Applications?

Can Traditional Programming Bridge the Ninja Performance Gap...

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39th annual International symposium on Computer Architecture (ISCA)

作者： Satish, Nadathur Kim, Changkyu Chhugani, Jatin Saito, Hideki Krishnaiyer, Rakesh Smelyanskiy, Mikhail Girkar, Milind Dubey, Pradeep Intel Corp Parallel Comp Lab Santa Clara CA 95051 USA Intel Corp Intel Compiler Lab Santa Clara CA 95051 USA

ISBN: (纸本)9781467304764

Current processor trends of integrating more cores with wider SIMD units, along with a deeper and complex memory hierarchy, have made it increasingly more challenging to extract performance from applications. It is believed by some that traditional approaches to programming do not apply to these modern processors and hence radical new languages must be discovered. In this paper, we question this thinking and offer evidence in support of traditional programming methods and the performance-vs-programming effort effectiveness of common multi-core processors and upcoming many-core architectures in delivering significant speedup, and close-to-optimal performance for commonly used parallel computing workloads. We first quantify the extent of the "Ninja gap", which is the performance gap between naively written C/C++ code that is parallelism unaware (often serial) and best-optimized code on modern multi-/many-core processors. Using a set of representative throughput computing benchmarks, we show that there is an average Ninja gap of 24X (up to 53X) for a recent 6-core Intel (R) Core (TM) i7 X980 Westmere CPU, and that this gap if left unaddressed will inevitably increase. We show how a set of well-known algorithmic changes coupled with advancements in modern compiler technology can bring down the Ninja gap to an average of just 1.3X. These changes typically require low programming effort, as compared to the very high effort in producing Ninja code. We also discuss hardware support for programmability that can reduce the impact of these changes and even further increase programmer productivity. We show equally encouraging results for the upcoming Intel (R) Many Integrated Core architecture (Intel (R) MIC) which has more cores and wider SIMD. We thus demonstrate that we can contain the otherwise uncontrolled growth of the Ninja gap and offer a more stable and predictable performance growth over future architectures, offering strong evidence that radical language changes are

关键词： parallel processing systems

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Pareto Optimal Temporal Partition Methodology for Reconfigurable architectures Based on Multi-objective Genetic Algorithm

Pareto Optimal Temporal Partition Methodology for Reconfigur...

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26th IEEE International parallel and Distributed Processing symposium (IPDPS)

作者： Sheng, Weiguang He, Weifeng Jiang, Jianfei Mao, Zhigang Shanghai Jiao Tong Univ Sch Microelect Shanghai 200030 Peoples R China

ISBN: (纸本)9780769546766

A pareto optimal temporal partition methodology was developed for splitting and mapping large data flow graph (DFG) to the coarse-grained reconfigurable architecture (CGRA). A multi-objective genetic algorithm (MOGA) derived from the SPEA-II algorithm was first time introduced to the temporal partition realm for simultaneously optimizing multiple mutually exclusive objectives. Experiments carried out on the ESL (electronic system level) model of the REmus processor show that MOGA based temporal partition algorithms is superior than heuristic algorithm by reducing execution delay 5%-28%, communication overheads 16%-37% without degradation the resource efficiency. Furthermore, comparisons with weight-based multi-objective simulated annealing algorithm show the pareto optimal algorithm can achieve slight better latency objective (3%), while dramatically decrease the communication overheads by at most 21% and the resource efficiency doesn't get worse.

关键词： Temporal Partition Pareto Optimal Coarse-grained Reconfigurable Multi-objective Genetic Algorithm

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