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检索条件"任意字段=Annual ACM Symposium on Parallel Algorithms and Architectures"

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Scheduling Irregular parallel Computations on Hierarchical Caches 11

Scheduling Irregular Parallel Computations on Hierarchical C...

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23rd annual symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Fineman, Jeremy T. Gibbons, Phillip B. Simhadri, Harsha Vardhan Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450307437

For nested-parallel computations with low depth (span, critical path length) analyzing the work, depth, and sequential cache complexity suffices to attain reasonably strong bounds on the parallel runtime and cache complexity on machine models with either shared or private caches. These bounds, however, do not extend to general hierarchical caches, due to limitations in (i) the cache-oblivious (CO) model used to analyze cache complexity and (ii) the schedulers used to map computation tasks to processors. This paper presents the parallel cache-oblivious (PCO) model, a relatively simple modification to the CO model that can be used to account for costs on a broad range of cache hierarchies. The first change is to avoid capturing artificial data sharing among parallel threads, and the second is to account for parallelism-memory imbalances within tasks. Despite the more restrictive nature of PCO compared to CO, many algorithms have the same asymptotic cache complexity bounds. The paper then describes a new scheduler for hierarchical caches, which extends recent work on "space-bounded schedulers" to allow for computations with arbitrary work imbalance among parallel subtasks. This scheduler attains provably good cache performance and runtime on parallel machine models with hierarchical caches, for nested-parallel computations analyzed using the PCO model. We show that under reasonable assumptions our scheduler is "work efficient" in the sense that the cost of the cache misses are evenly balanced across the processors-i.e., the runtime can be determined within a constant factor by taking the total cost of the cache misses analyzed for a computation and dividing it by the number of processors. In contrast, to further support our model, we show that no scheduler can achieve such bounds (optimizing for both cache misses and runtime) if work, depth, and sequential cache complexity are the only parameters used to analyze a computation.

关键词： parallel hierarchical memory Cost models Schedulers Analysis of parallel algorithms Cache complexity

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Brief announcement: RedRem: A parallel redundancy remover 11

Brief announcement: RedRem: A parallel redundancy remover

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Proceedings of the twenty-third annual acm symposium on parallelism in algorithms and architectures

作者： Acharya, Hrishikesh Gouda, Mohamed University of Texas at Austin Austin TX United States National Science Foundation Washington DC United States

ISBN: (纸本)9781450307437

Policies defined by a sequence of predicate-decision rules, with first-match semantics, are widely used;a notable example is their use in firewalls, where the rules are used to decide whether to accept or discard each packet. Owing to the critical importance of correctness of such policies, as well as the need for high performance, they have been the subject of considerable analysis. In earlier work, we have demonstrated that the problem of removing redundant rules from firewalls is theoretically equivalent to verifying that a firewall satisfies a property, and proposed that this theorem be used to build a high performance redundancy remover. In this paper, we realize this promise, and build a fast linear-space redundancy remover, one to three orders of magnitude faster than current approaches. Further, we show that our algorithm is easy to parallelize- there exists a natural way to partition a large instance of the problem into independent small ones. © 2011 Authors.

关键词： Redundancy

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Evaluating Graph Coloring on GPUs 11

Evaluating Graph Coloring on GPUs

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16th acm symposium on Principles and Practice of parallel Programming

作者： Grosset, A. V. Pascal Zhu, Peihong Liu, Shusen Venkatasubramanian, Suresh Hall, Mary Univ Utah Sch Comp Salt Lake City UT 84112 USA

ISBN: (纸本)9781450301190

This paper evaluates features of graph coloring algorithms implemented on graphics processing units (GPUs), comparing coloring heuristics and thread decompositions. As compared to prior work on graph coloring for other parallel architectures, we find that the large number of cores and relatively high global memory bandwidth of a GPU lead to different strategies for the parallel implementation. Specifically, we find that a simple uniform block partitioning is very effective on GPUs and our parallel coloring heuristics lead to the same or fewer colors than prior approaches for distributed-memory cluster architecture. Our algorithm resolves many coloring conflicts across partitioned blocks on the GPU by iterating through the coloring process, before returning to the CPU to resolve remaining conflicts. With this approach we get as few color (if not fewer) than the best sequential graph coloring algorithm and performance is close to the fastest sequential graph coloring algorithms which have poor color quality.

关键词： algorithms Performance Graph coloring parallel algorithm GPU CUDA

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Exploring the Tradeoffs between Programmability and Efficiency in Data-parallel Accelerators 11

Exploring the Tradeoffs between Programmability and Efficien...

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38th annual International symposium on Computer Architecture

作者： Lee, Yunsup Avizienis, Rimas Bishara, Alex Xia, Richard Lockhart, Derek Batten, Christopher Asanovic, Krste Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450304726

We present a taxonomy and modular implementation approach for data-parallel accelerators, including the MIMD, vector-SIMD, subword-SIMD, SIMT, and vector-thread (VT) architectural design patterns. We have developed a new VT microarchitecture, Maven, based on the traditional vector-SIMD microarchitecture that is considerably simpler to implement and easier to program than previous VT designs. Using an extensive design-space exploration of full VLSI implementations of many accelerator design points, we evaluate the varying tradeoffs between programmability and implementation efficiency among the MIMD, vector-SIMD, and VT patterns on a workload of microbenchmarks and compiled application kernels. We find the vector cores provide greater efficiency than the MIMD cores, even on fairly irregular kernels. Our results suggest that the Maven VT microarchitecture is superior to the traditional vector-SIMD architecture, providing both greater efficiency and easier programmability.

关键词： simplified vector-thread architectures vector-thread architectures maven data-parallel accelerators vt architectures simplified vt architectures

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Accelerating CUDA Graph algorithms at Maximum Warp 11

Accelerating CUDA Graph Algorithms at Maximum Warp

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16th acm symposium on Principles and Practice of parallel Programming

作者： Hong, Sungpack Kim, Sang Kyun Oguntebi, Tayo Olukotun, Kunle Stanford Univ Comp Syst Lab Stanford CA 94305 USA

ISBN: (纸本)9781450301190

Graphs are powerful data representations favored in many computational domains. Modern GPUs have recently shown promising results in accelerating computationally challenging graph problems but their performance suffers heavily when the graph structure is highly irregular, as most real-world graphs tend to be. In this study, we first observe that the poor performance is caused by work imbalance and is an artifact of a discrepancy between the GPU programming model and the underlying GPU architecture. We then propose a novel virtual warp-centric programming method that exposes the traits of underlying GPU architectures to users. Our method significantly improves the performance of applications with heavily imbalanced workloads, and enables trade-offs between workload imbalance and ALU underutilization for fine-tuning the performance. Our evaluation reveals that our method exhibits up to 9x speedup over previous GPU algorithms and 12x over single thread CPU execution on irregular graphs. When properly configured, it also yields up to 30% improvement over previous GPU algorithms on regular graphs. In addition to performance gains on graph algorithms, our programming method achieves 1.3x to 15.1x speedup on a set of GPU benchmark applications. Our study also confirms that the performance gap between GPUs and other multi-threaded CPU graph implementations is primarily due to the large difference in memory bandwidth.

关键词： algorithms Performance parallel graph algorithms CUDA GPGPU

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Dataflow execution of sequential imperative programs on multicore architectures 44

Dataflow execution of sequential imperative programs on mult...

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44th annual IEEE/acm symposium on Microarchitecture, MICRO 44

作者： Gupta, Gagan Sohi, Gurindar S. Computer Sciences Department University of Wisconsin-Madison Madison WI United States

ISBN: (纸本)9781450310536

As multicore processors become the default, researchers are aggressively looking for program execution models that make it easier to use the available resources. Multithreaded programming models that rely on statically-parallel programs have gained prevalence. Most of the existing research is directed at adapting and enhancing such models, alleviating their drawbacks, and simplifying their usage. This paper takes a different approach and proposes a novel execution model to achieve parallel execution of statically-sequential programs. It dynamically parallelizes the execution of suitably-written sequential programs, in a dataflow fashion, on multiple processing cores. Significantly, the execution is race-free and determinate. Thus the model eases program development and yet exploits available parallelism. This paper describes the implementation of a software runtime library that implements the proposed execution model on existing commercial multicore machines. We present results from experiments running benchmark programs, using both the proposed technique as well as traditional parallel programming, on three different systems. We find that in addition to easing the development of the benchmarks, the approach is resource-efficient and achieves performance similar to the traditional approach, using stock compilers, operating systems and hardware, despite the overheads of an all-software implementation of the model. © 2011 acm.

关键词： parallel programming

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Tight Bounds for parallel Randomized Load Balancing 43

Tight Bounds for Parallel Randomized Load Balancing

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43rd acm symposium on Theory of Computing

作者： Lenzen, Christoph Wattenhofer, Roger Swiss Fed Inst Technol Comp Engn & Networks Lab Zurich Switzerland

ISBN: (纸本)9781450306911

We explore the fundamental limits of distributed balls-intobins algorithms, i.e., algorithms where balls act in parallel, as separate agents. This problem was introduced by Adler et al., who showed that non-adaptive and symmetric algorithms cannot reliably perform better than a maximum bin load of Theta(log log n/log log log n) within the same number of rounds. We present an adaptive symmetric algorithm that achieves a bin load of two in log* n + O(1) communication rounds using O(n) messages in total. Moreover, larger bin loads can be traded in for smaller time complexities. We prove a matching lower bound of (1-o(1)) log* n on the time complexity of symmetric algorithms that guarantee small bin loads at an asymptotically optimal message complexity of O(n). The essential preconditions of the proof are (i) a limit of O(n) on the total number of messages sent by the algorithm and (ii) anonymity of bins, i.e., the port numberings of balls are not globally consistent. In order to show that our technique yields indeed tight bounds, we provide for each assumption an algorithm violating it, in turn achieving a constant maximum bin load in constant time. As an application, we consider the following problem. Given a fully connected graph of n nodes, where each node needs to send and receive up to n messages, and in each round each node may send one message over each link, deliver all messages as quickly as possible to their destinations. We give a simple and robust algorithm of time complexity O(log* n) for this task and provide a generalization to the case where all nodes initially hold arbitrary sets of messages. Completing the picture, we give a less practical, but asymptotically optimal algorithm terminating within O(1) rounds. All these bounds hold with high probability.

关键词： randomized allocation load balancing asymptotic bounds

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Preparing students for future architectures with an exploration of multi- and many-core performance 11

Preparing students for future architectures with an explorat...

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Proceedings of the 16th annual joint conference on Innovation and technology in computer science education

作者： Ernst, Daniel J. Department of Computer Science University of Wisconsin - Eau Claire Eau Claire WI 54702-4004 United States

ISBN: (纸本)9781450308878

The recent progression of modern computer architectures from serial to multi-core to many-core has raised numerous questions about the placement of parallel computing topics in undergraduate computer science curricula. While several papers have explored how programming and algorithms courses might introduce parallel programming topics, there has been very little discussion of the changes needed in computer organization and architecture coursework to help students understand key issues about the behavior of these platforms. To increase the relevance of these courses and to tackle more modern architectural issues, we propose extending the performance coverage of a traditional computer organization course to include an exploration of the quantitative characterization of a program's performance on a variety of architectural platforms, including modern GPU hardware. In this paper, we outline the changes made to the Computer Organization and Design course at University of Wisconsin - Eau Claire. These modifications included a 3 week unit on the basics of parallel and GPU architectures, along with a tiered project on program optimization. © 2011 acm.

关键词： parallel programming

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Performance Estimation Framework for Automated Exploration of CPU-Accelerator architectures 11

Performance Estimation Framework for Automated Exploration o...

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19th annual acm International symposium on Field-Programmable Gate Arrays

作者： Kenter, Tobias Plessl, Christian Platzner, Marco Kauschke, Michael Univ Paderborn Paderborn Ctr Parallel Comp Paderborn Germany

ISBN: (纸本)9781450305549

In this paper we present a fast and fully automated approach for studying the design space when interfacing reconfigurable accelerators with a CPU. Our challenge is, that a reasonable evaluation of architecture parameters requires a hardware/software partitioning that makes best use of each given architecture configuration. Therefore we developed a framework based on the LLVM infrastructure that performs this partitioning with high-level estimation of the runtime on the target architecture utilizing profiling information and code analysis. By making use of program characteristics also during the partitioning process, we improve previous results for various benchmarks and especially for growing interface latencies between CPU and accelerator.

关键词： llvm performance estimation hardware/software partitioning design space exploration

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parallel application memory scheduling 44

Parallel application memory scheduling

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44th annual IEEE/acm symposium on Microarchitecture, MICRO 44

作者： Ebrahimi, Eiman Miftakhutdinov, Rustam Fallin, Chris Lee, Chang Joo Joao, José A. Mutlu, Onur Patt, Yale N. Department of Electrical and Computer Engineering University of Texas Austin TX United States Carnegie Mellon University United States Intel Corporation United States

ISBN: (纸本)9781450310536

A primary use of chip-multiprocessor (CMP) systems is to speed up a single application by exploiting thread-level parallelism. In such systems, threads may slow each other down by issuing memory requests that interfere in the shared memory subsystem. This inter-thread memory system interference can significantly degrade parallel application performance. Better memory request scheduling may mitigate such performance degradation. However, previously proposed memory scheduling algorithms for CMPs are designed for multi-programmed workloads where each core runs an independent application, and thus do not take into account the inter-dependent nature of threads in a parallel application. In this paper, we propose a memory scheduling algorithm designed specifically for parallel applications. Our approach has two main components, targeting two common synchronization primitives that cause inter-dependence of threads: locks and barriers. First, the runtime system estimates threads holding the locks that cause the most serialization as the set of limiter threads, which are prioritized by the memory scheduler. Second, the memory scheduler shuffles thread priorities to reduce the time threads take to reach the barrier. We show that our memory scheduler speeds up a set of memory-intensive parallel applications by 12.6% compared to the best previous memory scheduling technique. © 2011 acm.

关键词： Locks (fasteners)

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