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Session details: parallel computing 11

Session details: Parallel computing

引用

Proceedings of the twenty-third annual acm symposium on parallelism in algorithms and architectures

作者： Geppino Pucci University of Padova

No abstract available.

ISBN: (纸本)9781450307437

No abstract available.

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TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-core Hybrid Transact...

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sonmez, Nehir Arcas, Oriol Pflucker, Otto Unsal, Osman S. Cristal, Adrian Hur, Ibrahim Singh, Satnam Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Spanish Natl Res Council Madrid Spain Microsoft Res Cambridge Cambridge England

ISBN: (纸本)9780769543017

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

关键词： Field programmable gate arrays Hardware MIPS R3000-compatible core MPSoC Multicore processing Proposals Registers Software TMbox TinySTM-ASF Virtex-5 FPGA electronic engineering computing field programmable gate arrays flexible 16-core hybrid transactional memory system flexible system logic design multicore design space multicore prototyping multiprocessing systems parallel programming parallel programming reconfigurable 16-core hybrid transactional memory system reconfigurable architectures reconfigurable computing system-on-chip transactional memory

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Efficient I/O for parallel visualization

Efficient I/O for parallel visualization

引用

11th Eurographics symposium on parallel Graphics and Visualization, EGPGV 2011

作者： Fogaly, Thomas Krügerz, Jens United States DFKI Intel VCI SCI Germany

ISBN: (纸本)9783905674323

While additional cores and newer architectures, such as those provided by GPU clusters, steadily increase available compute power, memory and disk access has not kept pace, and most believe this trend will continue. It is therefore of critical importance that we design systems and algorithms which make effective use of off-processor storage. This work details our experiences using parallel file systems, details performance using current systems and software, and suggests a new API which has greater potential for increased scalability. © The Eurographics Association 2011.

关键词： File organization

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Safe Nondeterminism in a Deterministic-by-Default parallel Language 11

Safe Nondeterminism in a Deterministic-by-Default Parallel L...

引用

38th symposium on Principles of Programming Languages

作者： Bocchino, Robert L., Jr. Heumann, Stephen Honarmand, Nima Adve, Sarita V. Adve, Vikram S. Welc, Adam Shpeisman, Tatiana Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450304900

A number of deterministic parallel programming models with strong safety guarantees are emerging, but similar support for non-deterministic algorithms, such as branch and bound search, remains an open question. We present a language together with a type and effect system that supports nondeterministic computations with a deterministic-by-default guarantee: nondeterminism must be explicitly requested via special parallel constructs (marked nd), and any deterministic construct that does not execute any nd construct has deterministic input-output behavior. Moreover, deterministic parallel constructs are always equivalent to a sequential composition of their constituent tasks, even if they enclose, or are enclosed by, nd constructs. Finally, in the execution of nd constructs, interference may occur only between pairs of accesses guarded by atomic statements, so then;are no data races, either between atomic statements and unguarded accesses (strong isolation) or between pairs of unguarded access (stronger than strong isolation alone). We enforce the guarantees at compile time with modular checking using novel,extensions to a previously described effect system. Our effect system extensions also enable the compiler to remove unnecessary transactional synchronization. We provide a static semantics, dynamic semantics, and a complete proof of soundness for the language;both with, and without the barrier removal feature. An experimental evaluation shows that our language can achieve good scalability for realistic parallel algorithms, and that the barrier removal techniques provide significant performance gains.

关键词： strong isolation transactional memory determinism atomicity effects parallel programming languages data race freedom tranasctions effect systems nondeterminism atomic sections

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FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities

FPGA Architecture of Generalized Laguerre-Volterra MIMO Mode...

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Li, Will X. Y. Cheung, Ray C. C. Zhang, Wei Chan, Rosa H. M. Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Dept Biomed Engn Los Angeles CA 90007 USA

ISBN: (纸本)9780769543017

We present a parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component;a second stage containing a pre-threshold potential updating unit with an error approximation function component;and a third stage consisting of a gradient calculation unit. A flexible and efficient architecture that can accommodate different design speed requirements are generated. Simulation results are rigorously analyzed. A hardware IP library for versatile models and applications is proposed. The design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a maximum clock rate of 357MHz, which is 4.37 x 10(5) times faster than the corresponding software model running on an AMD Pheono 9750 Quad Core Processor. It occupies 216,766 LUTs, maximum 12 block-RAMs, and 2016 DSP-blocks.

关键词： AMD Pheono 9750 Quad Core Processor Arrays Biological system modeling Computational modeling FPGA architecture Field programmable gate arrays Hardware MIMO systems Software Xilinx Virtex-6 FPGA biology computing error approximation function component field programmable gate arrays generalized Laguerre-Volterra MIMO model gradient calculation unit multiply and accumulation component neural nets neural population spiking activities parallel architectures parallelized architecture pipeline processing pipelined architecture time-varying neural dynamics vector convolution

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Component structure of the vacant set induced by a random walk on a random graph 11

Component structure of the vacant set induced by a random wa...

引用

annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Colin Cooper Alan Frieze Department of Computer Science King's College University of London Department of Mathematical Sciences Carnegie Mellon University

ISBN: (纸本)9780898719932

We consider random walks on two classes of random graphs and explore the likely structure of the set of unvisited vertices (or vacant set). Let Γ(t) be the subgraph induced by the vacant set. We show that for random graphs G_(n,p) above the connectivity threshold, and for random regular graphs G_r, for constant r≥3, there is a phase transition in the sense of the well-known Erdos-Renyi phase transition. Thus for t≤(1-ε)t~* we have a unique giant plus components of size O(log n) and for t≥(1+ε)t~* we have only components of size O(log n). In the case of G_r we describe the likely degree sequence and structure of the small (O(log n)) size components.

关键词： Component architectures Random walk Phase transtormations solidification Random Set (Psychology) Line graph

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Programming Real-Time Autofocus on a Massively parallel Reconfigurable Architecture Using Occam-pi

Programming Real-Time Autofocus on a Massively Parallel Reco...

引用

annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Zain-ul-Abdin Anders Ahlander Bertil Svensson Centre for Research on Embedded Systems (CERES) Halmstad University Halmstad Sweden Business Area Electronic Defence Systems Saab AB Gothenburg Sweden

Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. The design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. The feasability of this approach was illustrated by building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well-studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms. In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementing a significantly large case-study of focus criterion calculation in an auto focus algorithm on the Ambric architecture. Auto focus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developed and evaluated on the basis of performance. The comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. The two designs are, respectively, 29x and 40x more energy efficient.

关键词： Mobile communication Pixel Semantics Interpolation parallel processing Hardware Computer architecture

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annual acm symposium on parallelism in algorithms and architectures: Foreword

Annual ACM Symposium on Parallelism in Algorithms and Archit...

引用

annual acm symposium on parallelism in algorithms and architectures 2010年 iii页

作者： Phillips, Cynthia Sandia National Laboratories United States

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parallel Approximation algorithms for Facility-Location Problems 10

Parallel Approximation Algorithms for Facility-Location Prob...

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22nd acm symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Tangwongsan, Kanat Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450300797

This paper presents the design and analysis of parallel approximation algorithms for facility-location problems, including NC and RNC algorithms for (metric) facility location, k-center, k-median, and k-means These problems have received considerable attention during the past decades from the approximation algorithms community, which primarily concentrates on improving the approximation guarantees In this paper, we ask. Is it possible to parallelize some of the beautiful results from the sequential setting? Our starting point is a small, but diverse, subset of results in approximation algorithms for facility-location problems, with a primary goal of developing techniques for devising their efficient parallel counterparts. We focus on giving algorithms with low depth, near work efficiency (compared to the sequential versions), and low cache complexity

关键词： parallel algorithms approximation algorithms facility location problems

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Towards Optimizing Energy Costs of algorithms for Shared Memory architectures 10

Towards Optimizing Energy Costs of Algorithms for Shared Mem...

引用

22nd acm symposium on parallelism in algorithms and architectures

作者： Korthikanti, Vijay Anand Agha, Gul Univ Illinois Dept Comp Sci Urbana IL USA

ISBN: (纸本)9781450300797

Energy consumption by computer systems has emerged as an important concern However, the energy consumed in executing an algorithm cannot be inferred from its performance alone it must be modeled explicitly This paper analyzes energy consumption of parallel algorithms executed on shared memory multicore processors Specifically, we develop a methodology to evaluate how energy consumption of a given parallel algorithm changes as the number of cores and their frequency is varied We use this analysis to establish the optimal number of cores to minimize the energy consumed by the execution of a parallel algorithm for a specific problem size while satisfying a given performance requirement We study the sensitivity of our analysis to changes in parameters such as the ratio of the power consumed by a computation step versus the power consumed in accessing memory The results show that the relation between the problem size and the optimal number of cores is relatively unaffected for a wide range of these parameters.

关键词： Energy Performance parallel algorithms Shared Memory architectures

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