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检索条件"任意字段=Annual ACM Symposium on Parallel Algorithms and Architectures"

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Efficient discovery of loop nests in execution traces

Efficient discovery of loop nests in execution traces

引用

International symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

作者： Xu, Qiang Subhlok, Jaspal Hammen, Nathaniel CGGVeritas Inc. United States Department of Computer Science University of Houston United States

ISBN: (纸本)9780769541976

Execution and communication traces are central to performance modeling and analysis. Since the traces can be very long, meaningful compression and extraction of representative behavior is important. Commonly used compression procedures identify repeating patterns in sections of the input string and replace each instance with a representative symbol. This can prevent the identification of long repeating sequences corresponding to outer loops in a trace. This paper introduces and analyzes a framework for identifying the maximal loop nest from a trace. The discovery of loop nests makes construction of compressed representative traces straightforward. The paper also introduces a greedy algorithm for fast "near optimal" loop nest discovery with well defined bounds. Results of compressing MPI communication traces of NAS parallel benchmarks show that both algorithms identified the basic loop structures correctly. The greedy algorithm was also very efficient with an average processing time of 16.5 seconds for an average trace length of 71695 MPI events. © 2010 IEEE.

关键词： MPI communication traces NAS parallel benchmarks Trace compression application program interfaces execution traces greedy algorithm greedy algorithms loop discovery loop structures message passing near optimal loop nest discovery performance modeling program control structures repeating patterns repeating sequences

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A Model of Computation for MapReduce 10

A Model of Computation for MapReduce

引用

annual acm-Society for Industrial and Applied Mathmatics symposium on Discrete algorithms

作者： Howard Karloff Siddharth Suri Sergei Vassilvitskii AT&T Labs Yahoo

ISBN: (纸本)9780898717013

In recent years the MapReduce framework has emerged as one of the most widely used parallel computing platforms for processing data on terabyte and petabyte scales. Used daily at companies such as Yahoo!, Google, Amazon, and Facebook, and adopted more recently by several universities, it allows for easy parallelization of data intensive computations over many machines. One key feature of MapReduce that differentiates it from previous models of parallel computation is that it interleaves sequential and parallel computation. We propose a model of efficient computation using the MapReduce paradigm. Since MapReduce is designed for computations over massive data sets, our model limits the number of machines and the memory per machine to be substantially sublinear in the size of the input. On the other hand, we place very loose restrictions on the computational power of any individual machine - our model allows each machine to perform sequential computations in time polynomial in the size of the original input.

关键词： parallel PROCESSING (COMPUTERS) machine Terabyte arithmetic computational power Facebook Sequential universities

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Multiplier architectures for FPGA double precision functions (abstract only) 10

Multiplier architectures for FPGA double precision functions...

引用

Proceedings of the 18th annual acm/SIGDA international symposium on Field programmable gate arrays

作者： Y. Hamid Martin Langhammer Altera Corporation Penang Malaysia Altera Corporation High Wycombe United Kingdom

ISBN: (纸本)9781605589114

FPGA devices are now more capable at supporting floating point applications, but double precision IEEE754 systems are still very challenging to implement, with large amounts of logic, routing, and DSP resources needed. Double precision multiplier operators, requiring 54x54 multiplier cores, are now directly supported in the fabric, however, multiplier based algorithms for algebraic and elementary functions typically require larger multiplier functions, typically in excess of 60x60 bits precision. This paper will use the example of a double precision exp (ex) to explore tradeoffs with multiplier architectures mapped to current FPGAs devices. Different types of the larger multiplier architectures, including direct implementations and Karatsuba-Ofman algorithms will be compared, including their effect on the resource requirements and system performance of the exp function. Smaller multiplier architectures, which introduce a small maximum functional error, will also be *** large multiplier architectures can provide the same accuracy with increased system performance, with up to 33% less multiplier resources. Smaller multiplier will reduce the multiplier resources by up to 50%, albeit with a small maximum error, in the range of 5 ulp.

关键词： fpga floating point

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Brief Announcement: Performance Potential of an Easy-to-Program PRAM-On-Chip Prototype Versus State-of-the-Art Processor 09

Brief Announcement: Performance Potential of an Easy-to-Prog...

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21st acm symposium on parallelism in algorithms and architectures

作者： Caragea, George C. Saybasili, A. Beliz Wen, Xingzhi Vishkin, Uzi Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)9781605586069

we compare the Paraleap FPCA computer, a 64-processor hardware prototype of the PRAM-driven XMT architecture, with an Intel Core 2 Duo processor and show that Paraleap outperforms the Intel processor by up to 13.89x in terms of cycle counts. The comparison favors the Intel design, since the silicon area of an ASIC implementation of the 64-processor XMT design is the same as that of a single core.

关键词： paraleap parallel algorithms xmt PRAM explicit multi-treading ease of programming on-chip parallel processor

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Brief Announcement: Low Depth Cache-Oblivious Sorting 09

Brief Announcement: Low Depth Cache-Oblivious Sorting

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21st acm symposium on parallelism in algorithms and architectures

作者： Blelloch, Guy E. Gibbons, Phillip B. Simhadri, Harsha Vardhan Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781605586069

Cache-oblivious algorithms have the advantage of achieving good sequential cache complexity across all levels of a multi-level cache hierarchy, regardless of the specifies (cache size and cache line size) of each level. In this paper, we describe cache-oblivious sorting algorithms with optimal work, optimal cache complexity and polylogarithmic depth. Using known mappings, these lead to low cache complexities on shared-memory multiprocessors with a single level of private caches or a single shared cache. Moreover, the low cache complexities extend to shared-memory multiprocessors with common configurations of multi-level caches. The key factor in the low cache complexity on multiprocessors is the low depth of the algorithms we propose.

关键词： Cache-oblivious algorithms sorting parallel algorithms multiprocessors schedulers

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Inherent Limitations on Disjoint-Access parallel Implementations of Transactional Memory (Preliminary Version) 09

Inherent Limitations on Disjoint-Access Parallel Implementat...

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21st acm symposium on parallelism in algorithms and architectures

作者： Attiya, Hagit Hillel, Eshcar Milani, Alessia Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel

ISBN: (纸本)9781605586069

Transactional memory (TM) is a promising approach for designing concurrent data structures, and it is essential to develop better understanding of the formal properties that can be achieved by TM implementations. Two fundamental properties of TM implementations are disjoint-access parallelism, which is critical for their scalability, and the invisibility of read operations, which reduces memory contention. This paper proves an inherent tradeoff for implementations of transactional memories: they cannot be both disjoint-access parallel and have read-only transactions that are invisible and always terminate successfully. In fact, a lower bound of Omega(t) is proved on the number of writes needed in order to implement a read-only transaction of t items, which successfully terminates in a disjoint-access parallel TM implementation. The results assume strict serializability and thus hold under the assumption of opacity. It is shown how to extend the results to hold also for weaker consistency conditions, serializability and snapshot isolation.

关键词： Transactional memory disjoint-access parallelism partial snapshots lower bound impossibility result

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parallel Sparse Matrix-Vector and Matrix-Transpose-Vector Multiplication Using Compressed Sparse Blocks 09

Parallel Sparse Matrix-Vector and Matrix-Transpose-Vector Mu...

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21st acm symposium on parallelism in algorithms and architectures

作者： Buluc, Aydin Fineman, Jeremy T. Frigo, Matteo Gilbert, John R. Leiserson, Charles E. Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

ISBN: (纸本)9781605586069

This paper introduces a storage format for sparse matrices, called compressed sparse blocks (CSB), which allows both Ax and A(x)(inverted perpendicular) to be computed efficiently in parallel, where A is an n x n sparse matrix with nnz >= n nonzeros and x is a dense n-vector. Our algorithms use Theta(nnz) work (serial running time) and Theta(root nlgn) span (critical-path length), yielding a parallelism of Theta(nnz/root nlgn), which is amply high for virtually any large matrix. The storage requirement for CSB is esssentially the same as that for the more-standard compressed-sparse-rows (CSR) format, for which computing Ax in parallel is easy but A(x)(inverted perpendicular) is difficult. Benchmark results indicate that on one processor, the CSB algorithms for Ax and A(x)(inverted perpendicular) run just as fast as the CSR algorithm for Ax, but the CSB algorithms also scale up linearly with processors until limited by off-chip memory bandwidth.

关键词： Compressed sparse blocks compressed sparse columns compressed sparse rows matrix transpose matrix-vector multiplication multithreaded algorithm parallelism span sparse matrix storage format work

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SPAA'09 - Proceedings of the 21st annual symposium on parallelism in algorithms and architectures

SPAA'09 - Proceedings of the 21st Annual Symposium on Parall...

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21st annual symposium on parallelism in algorithms and architectures, SPAA'09

ISBN: (纸本)9781605586069

The proceedings contain 43 papers. The topics discussed include: speed scaling of processes with arbitrary speedup curves on a multiprocessor;the bell is ringing in speed-scaled multiprocessor scheduling;mapping filtering streaming applications with communication costs;scheduling to minimize staleness and stretch in real-time data warehouses;parameterized maximum and average degree approximation in topic-based publish-subscribe overlay network design;selfishness in transactional memory;at-most-once semantics in asynchronous shared memory;memory models: a case for rethinking parallel languages and hardware;the life and times of a ZooKeeper;Cassandra - a structured storage system on a P2P network;Pregel: a system for large-scale graph processing;towards transactional memory semantics for C++;on avoiding spare aborts in transactional memory;inherent limitations on disjoint-access parallel implementations of transactional memory;reducers and other Cilk++ hyperobjects;and beyond nested parallelism: tight bounds on work-stealing overheads for parallel futures.

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Field-Split parallel Architecture for High Performance Multi-Match Packet Classification Using FPGAs 09

Field-Split Parallel Architecture for High Performance Multi...

引用

21st acm symposium on parallelism in algorithms and architectures

作者： Jiang, Weirong Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781605586069

Multi-match packet classification is a critical function in network intrusion detection systems (NIDS), where all matching rules for a packet need to be reported. Most of the previous work is based on ternary content addressable memories (TCAMs) which are expensive and are not scalable with respect to clock rate, power consumption, and circuit area. This paper studies the characteristics of real-life Snort NIDS rule sets, and proposes a novel SRAM-based architecture. The proposed architecture is called field-split parallel bit vector (FSBV) where some header fields of a packet are further split into bit-level subfields. Unlike previous multi-match packet classification algorithms which suffer from memory explosion, the memory requirement of FSBV is linear in the number of rules. FPGA technology is exploited to provide high throughput and to support dynamic updates. Implementation results show that our architecture can store on a single Xilinx Virtex-5 FPGA the full set of packet header rules extracted from the latest Snort NIDS and sustains 100 Gbps throughput for minimum size (40 bytes) packets. The design achieves 1.25x improvement in throughput while the power consumption is approximately one fourth that of the state-of-the-art solutions.

关键词： FPGA multi-match packet classification NIDS SRAM

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Beyond Nested parallelism: Tight Bounds on Work-Stealing Overheads for parallel Futures 09

Beyond Nested Parallelism: Tight Bounds on Work-Stealing Ove...

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21st acm symposium on parallelism in algorithms and architectures

作者： Spoonhower, Daniel Blelloch, Guy E. Gibbons, Phillip B. Harper, Robert Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781605586069

Work stealing is a popular method of scheduling fine-grained parallel tasks. The performance of work stealing has been extensively studied, both theoretically and empirically, but primarily for the restricted class of nested-parallel (or fully strict) computations. we extend this prior work by considering a broader class of programs that also supports pipelined parallelism through the use of parallel futures. Though the overhead of work-stealing schedulers is often quantified in terms of the number of steals, we show that a broader metric, the number of deviations, is a better way to quantify work-stealing overhead for less restrictive forms of parallelism, including parallel futures. For such parallelism, we prove bounds on work-stealing overheads-scheduler time and cache misses-as a function of the number of deviations Deviations can occur, for example, when work is stolen or when a future is touched. We also show instances where deviations can occur independently of steals and touches. Next, we prove that, under work stealing, the expected number of deviations is O(Pd+td) in a P-processor execution of a computation with span d and t touches of futures. Moreover, this bound is existentially tight for any work-stealing scheduler that is parsimonious (those where processors steal only when their queues are empty);this class includes all prior work-stealing schedulers. We also present empirical measurements of the number of deviations incurred by a classic application of futures, Halstead's quicksort, using our parallel implementation of ML. Finally, we identify a family of applications that use futures and, in contrast to quicksort, incur significantly smaller overheads.

关键词： scheduling work stealing futures performance bounds

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