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36th International symposium on Microarchitecture

作者： Swanson, S Michelson, K Schwerin, A Oskin, M Univ Washington Seattle WA 98195 USA

ISBN: (纸本)076952043X

Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge. Ever increasing wire-delay relative to switching speed and the exponential cost of circuit complexity make simply scaling up existing processor designs futile. In this paper, we present an alternative to superscalar design, WaveScalar. WaveScalar is a dataflow instruction set architecture and execution model designed for scalable, low-complexity/high-performance processors. WaveScalar is unique among dataflow architectures in efficiently providing traditional memory semantics. At last, a dataflow machine can run "real-world" programs, written in any language, without sacrificing parallelism. The WaveScalar ISA is designed to run on an intelligent memory system. Each instruction in a WaveScalar binary executes in place in the memory system and explicitly communicates with its dependents in dataflow fashion. WaveScalar architectures cache instructions and the values they operate on in a WaveCache, a simple grid of "alu-in-cache" nodes. By co-locating computation and data in physical space, the WaveCache minimizes long wire, high-latency communication. This paper introduces the WaveScalar instruction set and evaluates a simulated implementation based on current technology. Results for the SPEC and Mediabench applications demonstrate that the WaveCache out-performs an aggressively configured superscalar design by 2-7 times, with ample opportunities for future optimizations.

关键词： Availability Complexity theory Costs Instruction sets Intelligent systems parallel processing Process design Silicon Space technology Switching circuits

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On spectral bounds for the k-partitioning of graphs

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THEORY OF COMPUTING SYSTEMS 2003年第5期36卷 461-478页

作者： Elsässer, R Lücking, T Monien, B Univ Gesamthsch Paderborn Dept Comp Sci D-33102 Paderborn Germany

When executing processes on parallel computer systems a major bottleneck is interprocessor communication. One way to address this problem is to minimize the communication between processes that are mapped to different processors. This translates to the k-partitioning problem of the corresponding process graph, where k is the number of processors. The classical spectral lower bound of (\V\/2k) Sigma(i=1)(k)lambda(i) for the k-section width of a graph is well known. We show new relations between the structure and the eigenvalues of a graph and present a new method to get tighter lower bounds on the k-section width. This method makes use of the level structure defined by the k-section. We define a global expansion property and prove that for graphs with the same k-section width the spectral lower bound increases with this global expansion. We also present examples of graphs for which our new bounds are tight up to a constant factor.

关键词： Lower bound level structure Line graph parallel computers eigenvalues section width interprocessor communication Bound PROCESSOR

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36th International symposium on Microarchitecture

36th International Symposium on Microarchitecture

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IEEE/acm International symposium on Microarchitecture (MICRO)

The following topics are dealt with: voltage scaling; transient faults; cache design; power efficient architectures; energy efficient architectures; application specific optimization; dynamic optimization systems; dynamic program analysis; dynamic program optimization; branch optimization; value optimization; scheduling optimizations; dataflow architectures; data parallel architectures; clustered architectures; network processors; and scaling design.

关键词： Microprocessors Computer instructions Voltage control Transient analysis Cache memories Optimization methods Data flow graphs Data flow computing Processor scheduling parallel architectures

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Compiler optimization-space exploration

Compiler optimization-space exploration

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International symposium on Code Generation and Optimization

作者： Triantafyllis, S Vachharajani, M Vachharajani, N August, DI Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)076951913X

To meet the demands of modem architectures, optimizing compilers must incorporate an ever larger number of increasingly complex transformation algorithms. Since code transformations may often degrade performance or interfere with subsequent transformations, compilers employ predictive heuristics to guide optimizations by predicting their effects a priori. Unfortunately, the unpredictability of optimization interaction and the irregularity of today's wide-issue machines severely limit the accuracy of these heuristics. As a result, compiler writers may temper high variance optimizations with overly conservative heuristics or may exclude these optimizations entirely. While this process results in a compiler capable of generating good average code quality across the target benchmark set, it is at the cost of missed optimization opportunities in individual code segments. To replace predictive heuristics, researchers have proposed compilers which explore many optimization options, selecting the best one a posteriori. Unfortunately, these existing iterative compilation techniques are not practical for reasons of compile time and applicability. In this paper we present the Optimization-Space Exploration (OSE) compiler organization, the first practical iterative compilation strategy applicable to optimizations in general-purpose compilers. Instead of replacing predictive heuristics, OSE uses the compiler writer's knowledge encoded in the heuristics to select a small number of promising optimization alternatives for a given code segment. Compile time is limited by evaluating only these alternatives for hot code segments using a general compile-time performance estimator An OSE-enhanced version of Intel's highly-tuned, aggressively optimizing production compiler for IA-64 yields a significant performance improvement, more than 20% in some cases, on Itanium for SPEC codes.

关键词： Computer architecture Computer science Cost function Degradation Microarchitecture Optimizing compilers parallel processing Performance gain Production Resource management

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Universal mechanisms for data-parallel architectures 36

Universal mechanisms for data-parallel architectures

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Karthikeyan Sankaralingam S.W. Keckler W.R. Mark D. Burger Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin USA

ISBN: (纸本)9780769520438

Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper presents a classification scheme for data-parallel program attributes, and proposes micro-architectural mechanisms to support applications with diverse behavior for using a single reconfigurable architecture. We focus on the following four broad kinds of data-parallel programs - DSP/multimedia, scientific, networking, and real-time graphics workloads. While all of these programs exhibit high computational intensity, coarse-grain regular control behavior, and some regular memory access behavior, they show wide variance in the computation requirements, fine grain control behavior, and the frequency of other types of memory accesses. Based on this study of application attributes, this paper proposes a set of general micro-architectural mechanisms that enable a baseline architecture to be dynamically tailored to the demands of a particular application. These mechanisms provide efficient execution across a spectrum of data-parallel application and can be applied to diverse architectures ranging from vector cores to conventional superscalar cores. Our results using a baseline TRIPS processor show that the configurability of the architecture to the application demands provides harmonic mean performance improvement of 5%-55% over scalable yet less flexible architectures, and performs competitively against specialized architectures.

关键词： Computer architecture Graphics Hardware Application software Computational modeling Communication system control Digital signal processing chips Engines Laboratories Reconfigurable architectures

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Optimal parallel selection 03

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Proceedings of the fourteenth annual acm-SIAM symposium on Discrete algorithms

作者： Yijie Han University of Missouri at Kansas City Kansas City MO

We present an optimal parallel selection algorithm on the EREW PRAM. This algorithm runs in O(log n) time with n/log n processors. This complexity matches the known lower bound for parallel selection on the EREW PRAM ... 详细信息

ISBN: (纸本)9780898715385

关键词： selection EREW PRAM parallel algorithms

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WaveScalar 36

WaveScalar

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： S. Swanson K. Michelson A. Schwerin M. Oskin Computer Science and Engineering University of Washington USA

ISBN: (纸本)9780769520438

Silicon technology continues to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge. Ever increasing wire-delay relative to switching speed and the exponential cost of circuit complexity make simply scaling up existing processor designs futile. In this paper, we present an alternative to superscalar design, WaveScalar. WaveScalar is a dataflow instruction set architecture and execution model designed for scalable, low-complexity/high performance processors. WaveScalar is unique among dataflow architectures in efficiently providing traditional memory semantics. At last, a dataflow machine can run "real-world" programs, written in any language, without sacrificing parallelism. The WaveScalar ISA is designed to run on an intelligent memory system. Each instruction in a WaveScalar binary executes in place in the memory system and explicitly communicates with its dependents in dataflow fashion. WaveScalar architectures cache instructions and the values they operate on in a WaveCache, a simple grid of "alu-in-cache" nodes. By co-locating computation and data in physical space, the WaveCache minimizes long wire, high-latency communication. This paper introduces the WaveScalar instruction set and evaluates a simulated implementation based on current technology. Results for the SPEC and Mediabench applications demonstrate that the WaveCache out-performs an aggressively configured superscalar design by 2-7 times, with ample opportunities for future optimizations.

关键词： Space technology Silicon Availability Switching circuits Costs Complexity theory Process design parallel processing Instruction sets Intelligent systems

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Performance and area modeling of complete FPGA designs in the presence of loop transformations

Performance and area modeling of complete FPGA designs in th...

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annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： K.R.S. Shayee Joonseok Park P.C. Diniz Department of Electrical Engineering Systems Division University of Southern California Los Angeles CA USA USC Information Sciences Institute CA USA

Digital image processing algorithms are a good match for direct implementation on FPGAs as current FPGA architectures can naturally match the fine grain parallelism in these applications. Typically, these algorithms are structured as a sequence of operations, expressed in high-level programming languages as tight loop nests. The loops usually define a shifting-window region over which the algorithm applies a simple localized operator (e.g., a differential gradient, or a min/max). In this research we focus on the development of fast, yet accurate performance and area modeling of complete FPGA designs that combine analytical, empirical and behavioral estimation techniques. We model the application of a set of important program transformations for image processing algorithms, namely loop unrolling, tiling, loop interchanging, loop fission and array privatization, and explore pipelined and non-pipelined execution modes. We take into consideration the impact of various transformations, in the presence of limited I/O resources like address generators and external memory data channels, on the performance of a complete design implemented in a FPGA based architecture.

关键词： Field programmable gate arrays parallel processing Computer languages Hardware Bandwidth Information analysis Performance analysis Image processing Delay Read-write memory

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Beating in-order stalls with "flea-flicker" two-pass pipelining

Beating in-order stalls with "flea-flicker" two-pass pipelin...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： R.D. Barnes S.J. Patel E.M. Nystrom N. Navarro J.W. Sias W.W. Hwu Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign USA

Accommodating the uncertain latency of load instructions is one of the most vexing problems in in-order microarchitecture design and compiler development. Compilers can generate schedules with a high degree of instruction-level parallelism but cannot effectively accommodate unanticipated latencies; incorporating traditional out-of-order execution into the microarchitecture hides some of this latency but redundantly performs work done by the compiler and adds additional pipeline stages. Although effective techniques, such as prefetching and threading, have been proposed to deal with anticipable, long latency misses, the shorter, more diffuse stalls due to difficult-to-anticipate, first- or second-level misses are less easily hidden on in-order architectures. This paper addresses this problem by proposing a microarchitectural technique, referred to as two-pass pipelining, wherein the program executes on two in-order back-end pipelines coupled by a queue. The "advance" pipeline executes instructions greedily, without stalling on unanticipated latency dependences (executing independent instructions while otherwise blocking instructions are deferred). The "backup" pipeline allows concurrent resolution of instructions that were deferred in the other pipeline, resulting in the absorption of shorter misses and the overlap of longer ones. This paper argues that this design is both achievable and a good use of transistor resources and shows results indicating that it can deliver significant speedups for in-order processor designs.

关键词： Pipeline processing Delay Microarchitecture Processor scheduling Runtime Computer aided instruction Out of order Registers parallel processing Process design

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Two techniques for reconciling algorithm parallelism with memory constraints (extended abstract)

Two techniques for reconciling algorithm parallelism with me...

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Fourteenth annual acm symposium on parallel algorithms and architectures

作者： Vishkin, Uzi University of Maryland College Park MD United States

The utility of algorithm parallelism for coping with increased processor to memory latencies using "latency hiding" is part of the folklore of parallel computing. Latency hiding techniques increase the traffic to memory and therefore may "hit another wall": limited bandwidth to memory. The current paper attempts to stimulate research in the following general direction: show that algorithm parallelism need not conflict with limited bandwidth. A general technique for using parallel algorithms to enhance serial implementation in the face of processor-memory latency problems is revisited. Two techniques for alleviating memory bandwidth constraints are presented. Both techniques can be incorporated in a compiler. There is often considerable parallelism in many of the algorithms which are known as useful serial algorithms. Interestingly enough, all the examples provided for the use of the two techniques come from such serial algorithms.

关键词： parallel processing systems

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