Welcome to the 16th workshop on interactionbetweencompilers and computerarchitectures (INTERACT-16), held on February 25, 2012, in New Orleans, Louisiana. This year, the workshop was held in conjunction with the 18...
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The proceedings contain 10 papers. The topics discussed include: compiling for fine-grain concurrency: planning and performing software thread integration;dynamically scheduling VLIW instructions with dependency infor...
ISBN:
(纸本)0769515347
The proceedings contain 10 papers. The topics discussed include: compiling for fine-grain concurrency: planning and performing software thread integration;dynamically scheduling VLIW instructions with dependency information;accuracy of profile maintenance in optimizing compilers;mastering startup costs in assembler-based compiled instruction-set simulation;on the predictability of program behavior using different input data sets;quantitative evaluation of the register stack engine and optimizations for future Itanium processors;a study on data allocation of on-chip dual memory banks;code size efficiency in global scheduling for ILP processors;code compression by register operand dependency;and code cache management schemes for dynamic optimizers.
The proceedings contain 9 papers. The topics discussed include: compiler analysis for trace-level speculative multithreaded architectures;multigrain parallel processing on compiler cooperative chip multiprocessor;an e...
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ISBN:
(纸本)0769523218
The proceedings contain 9 papers. The topics discussed include: compiler analysis for trace-level speculative multithreaded architectures;multigrain parallel processing on compiler cooperative chip multiprocessor;an empirical study of data speculation use on the Intel Itanium 2 processor;analysis of path planning information generated with performance monitoring hardware;cooperative caching with keep-me and evict-me;hybrid compiler and microarchitecture technique for cache traffic optimization;a tile size selection analysis for blocked array layouts;automatic low overhead program instrumentation with the LOPI framework;and optimizing structures in object oriented programs.
The proceedings contain 9 papers. The topics discussed include: impact of JIT/JVM optimizations on java application performance;compiler support for dynamic speculative pre-execution;procedure cloning and integration ...
ISBN:
(纸本)0769518893
The proceedings contain 9 papers. The topics discussed include: impact of JIT/JVM optimizations on java application performance;compiler support for dynamic speculative pre-execution;procedure cloning and integration for converting parallelism from coarse to fine grain;high performance code generation through lazy activation records;the effect of compiler optimizations on Pentium 4 power consumption;combining software and hardware monitoring for improved power and performance tuning;a region-based compilation infrastructure;and compiler-directed resource management for active code regions.
The following topics are dealt with: compilers and computerarchitectures; instruction scheduling; simulation and profiling; data access; and code size.
ISBN:
(纸本)0769515347
The following topics are dealt with: compilers and computerarchitectures; instruction scheduling; simulation and profiling; data access; and code size.
The proceedings contain 6 papers. The topics discussed include: doubling the number of registers on arm processors;enhancing LRU replacement via phantom associativity;MGC: multiple graph-coloring for non-volatile memo...
ISBN:
(纸本)9781467326148
The proceedings contain 6 papers. The topics discussed include: doubling the number of registers on arm processors;enhancing LRU replacement via phantom associativity;MGC: multiple graph-coloring for non-volatile memory based hybrid scratchpad memory;understand and categorize dynamically dead instructions for contemporary architectures;cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids;and lazy reference counting for the microgrid.
The proceedings contain 10 papers. The topics discussed include: a co-designed HW/SW approach to general purpose program acceleration using a programmable functional unit;the good block: hardware/software design for c...
ISBN:
(纸本)9780769544410
The proceedings contain 10 papers. The topics discussed include: a co-designed HW/SW approach to general purpose program acceleration using a programmable functional unit;the good block: hardware/software design for composable, block-atomic processors;improving low power processor efficiency with static pipelining;a constraint programming approach for instruction assignment;on-line trace based automatic parallelization of Java programs on multicore platforms;MATLAB parallelization through scalarization;JIT compilation policy on single-core and multi-core machines;characterizing the performance and energy efficiency of lock-free data structures;implications of program phase behavior on timing analysis;and aggressive function splitting for partial inlining.
The proceedings contains 12 papers from the Eight workshop on interactionbetweencompilers and computerarchitectures, INTERACT-8 2004. Topics discussed include: data movement optimization for software-controlled on-...
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ISBN:
(纸本)0769520618
The proceedings contains 12 papers from the Eight workshop on interactionbetweencompilers and computerarchitectures, INTERACT-8 2004. Topics discussed include: data movement optimization for software-controlled on-chip memory;reducing fetch architecture complexity using procedure inlining;fast indexing for blocked array layouts to improve multi-level cache locality;exploiting procedure level locality to reduce instruction cache misses;energy-efficiency potential of a phase-based cache resizing scheme for embedded systems;link-time optimization techniques for eliminating conditional branch redundancies;and garbage collector refinement for new dynamic multimedia applications on embedded systems.
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