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共 113 条记录，以下是91-100 订阅

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Dynamically scheduling VLIW instructions with dependency information

Dynamically scheduling VLIW instructions with dependency inf...

引用

annual workshop on interaction between compilers and computer architectures

作者： Sunghyun Jee K. Palaniappan Cheonan College of Foreign Studies Chonan Chungcheongnam South Korea University of Missouri Columbia MO USA

ISBN: (纸本)0769515347

The paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing dynamically scheduled Very Long Instruction Word (VLIW) instructions. Dynamically Instruction Scheduled VLIW (DISVLIW) processor is aimed specifically at dynamic scheduling VLIW instructions with dependency information. The DISVLIW processor dynamically schedules each instruction within long instructions using functional unit and dynamic scheduler pairs. Every dynamic scheduler dynamically checks for data dependencies and resource collisions while scheduling each instruction. This scheduling is especially effective in applications containing loops. We simulate the architecture and show that the DISVLIW processor performs significantly better than the VLIW processor for a wide range of cache sizes and across various numerical benchmark applications.

关键词： Dynamic scheduling VLIW Processor scheduling Clocks computer architecture Educational institutions Conferences Pipelines Parallel processing Decoding

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Profitable loop fusion and tiling using model-driven empirical search 06

Profitable loop fusion and tiling using model-driven empiric...

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20th annual International Conference on Supercomputing, ICS 2006

作者： Qasem, Apan Kennedy, Ken Department of Computer Science Rice University Houston TX 77005 United States

ISBN: (纸本)1595932828

Loop fusion and tiling are both recognized as effective transformations for improving memory performance of scientific applications. However, because of their sensitivity to the underlying cache architecture and their interaction with each other it is difficult to determine a good heuristic for applying these transformations profitably across architectures. In this paper, we present a model-guided empirical tuning strategy for profitable application of loop fusion and tiling. Our strategy consists of a detailed cost model that characterizes the interaction between the two transformations at different levels of the memory hierarchy. The novelty of our approach is in exposing key architectural parameters within the model for automatic tuning through empirical search. Preliminary experiments with a set of applications on four different platforms show that our strategy achieves significant performance improvement over fully optimized code generated by state-of-the-art commercial compilers. The time spent in searching for the best parameters is considerably less than with other search strategies. Copyright 2006 ACM.

关键词： Storage allocation (computer)

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Code compression by register operand dependency

Code compression by register operand dependency

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annual workshop on interaction between compilers and computer architectures

作者： K. Lin J. Jyh-Jiun Shann Chung-Ping Chung Department of Computer Science & Information Engineering National Chiao Tung University Taiwan

ISBN: (纸本)0769515347

This paper proposes a dictionary-based code compression technique that maps the source register operands to the nearest occurrence of a destination register in the predecessor instructions. The key idea is that most destination registers have great potential to be used as source registers in the following instructions. The dependent registers can be removed from the dictionary if this information can be specified otherwise. As a result, the compression ratio benefits from the decreased dictionary size. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.6% on average for MediaBench benchmarks compiled for MIPS R2000 processor.

关键词： Registers Costs Dictionaries Kelvin Read only memory Application specific integrated circuits Silicon Power generation economics Environmental economics High level languages

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Implications of Program Phase Behavior on Timing Analysis

Implications of Program Phase Behavior on Timing Analysis

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annual workshop on interaction between compilers and computer architectures

作者： Archana Ravindar Y.N. Srikant Department of Computer Science and Automation Indian Institute of Science Bangalore India

Knowledge about program worst case execution time (WCET) is essential in validating real-time systems and helps in effective scheduling. One popular approach used in industry is to measure execution time of program components on the target architecture and combine them using static analysis of the program. Measurements need to be taken in the least intrusive way in order to avoid affecting accuracy of estimated WCET. Several programs exhibit phase behavior, wherein program dynamic execution is observed to be composed of phases. Each phase being distinct from the other, exhibits homogeneous behavior with respect to cycles per instruction (CPI), data cache misses etc. In this paper, we show that phase behavior has important implications on timing analysis. We make use of the homogeneity of a phase to reduce instrumentation overhead at the same time ensuring that accuracy of WCET is not largely affected. We propose a model for estimating WCET using static worst case instruction counts of individual phases and a function of measured average CPI. We describe a WCET analyzer built on this model which targets two different architectures. The WCET analyzer is observed to give safe estimates for most benchmarks considered in this paper. The tightness of the WCET estimates are observed to be improved for most benchmarks compared to Chronos, a well known static WCET analyzer.

关键词： computer architecture Timing Phase measurement Instruments Accuracy Benchmark testing Analytical models

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An adiabatic framework for a low energy /spl mu/-architecture and compiler

An adiabatic framework for a low energy /spl mu/-architectur...

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annual workshop on interaction between compilers and computer architectures

作者： P. Ramarao A. Tyagi Department of Electrical & Computer Engineering Iowa State University Ames IA USA

We add new passes to the MachineSUIF compiler, to flag instruction groups that can potentially walk through a superscalar pipeline as a group. Hence, these instruction groups offer a fairly robust model of superscalar microarchitecture ILP. A compile time scheduling analysis can also generate instruction slack values. The slack indicates the program region within which an instruction can be scheduled. We also present a dispatch stage dynamic scheduling algorithm that utilizes the compiler annotated slacks to reschedule instructions with the explicit objective of minimizing the dispatch stage IPC variance. In other words, the proposed dispatch stage is adiabatic. Preliminary experimental results demonstrate an average reduction of 4.16% in IPC variance over SPEC2000 benchmarks with the adiabatic compiler and microarchitecture. The preliminary evaluation also shows the average processor dispatch stage energy reduction of 3.9% over the same SPEC2000 benchmarks. We expect to add similar IPC smoothening control knobs at instruction fetch and issue stages as well in the future, which should result in a more significant energy reduction.

关键词： Pipelines computer architecture Switches Microarchitecture Capacitance Power engineering and energy Thermodynamics Temperature Zero voltage switching Program processors

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Multigrain parallel processing on compiler cooperative chip multiprocessor

Multigrain parallel processing on compiler cooperative chip ...

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annual workshop on interaction between compilers and computer architectures

作者： K. Kimura Y. Wada H. Nakano T. Kodaka J. Shirako K. Ishizaka H. Kasahara Department of Computer Science Waseda University Tokyo Japan

This paper describes multigrain parallel processing on a compiler cooperative chip multiprocessor. The multigrain parallel processing hierarchically exploits multiple grains of parallelism such as coarse grain task parallelism, loop iteration level parallelism and statement level near-fine grain parallelism. The chip multiprocessor has been designed to attain high effective performance, cost effectiveness and high software productivity by supporting the optimizations of the multigrain parallelizing compiler, which is developed by Japanese Millennium Project IT21 "Advance Parallelizing Compiler". To achieve full potential of multigrain parallel processing, the chip multiprocessor integrates simple single-issue processors having distributed shared data memory for both optimal use of data locality and scalar data transfer, local data memory for processor private data, in addition to centralized shared memory for shared data among processors. This paper focuses on the scalability of the chip multiprocessor having up to eight processors on a chip by exploiting of the multigrain parallelism from SPECfp95 programs. When microSPARC like the simple processor core is used under assumption of 90 nm technology and 2.8 GHz, the evaluation results show the speedups for eight processors and four processors reach 7.1 and 3.9, respectively. Similarly, when 400 MHz is assumed for embedded usage, the speedups reach 7.8 and 4.0, respectively.

关键词： Parallel processing computer architecture Scalability Productivity Collaborative work Wiring Delay Embedded computing High performance computing Personal digital assistants

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JIT Compilation Policy on Single-Core and Multi-core Machines

JIT Compilation Policy on Single-Core and Multi-core Machine...

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annual workshop on interaction between compilers and computer architectures

作者： Prasad A Kulkarni Jay Fuller Department of Electrical Engineering and Computer Science University of Kansas Lawrence KS USA

Dynamic or Just-in-Time (JIT) compilation is crucial to achieve acceptable performance for applications written in traditionally interpreted languages, such as Java and C#. Such languages enable the generation of portable applications that are written and compiled once, and can be executed by a virtual machine on any supported architecture. However, by virtue of occurring at runtime, dynamic compilation adds to the overall execution time of the application, and can potentially slow down program execution if performed injudiciously. Selective compilation is a technique that was developed for single-core architectures to manage the compilation overhead by dynamically determining and compiling only the most critical program regions. Current processors have evolved from single-core machines to those supporting multiple tightly-integrated cores. Consequently, research is needed to explore the best JIT compilation policy on multi-core machines with several concurrent compiler threads. In this paper, we present novel experimental configurations to understand the benefits of dynamic compilation, and find the best JIT compilation policies on single and multi-core machines. Our results validate earlier claims that compiling a small percentage of methods has an inordinately large impact on performance. We show that spawning a greater number of simultaneous compiler threads can achieve better program performance on single-core machines. Our results also reveal that more than an increase in compiler aggressiveness, a small increase in the number of compiler threads achieves the best application performance on multi-core machines.

关键词： Benchmark testing Dynamic compiler Virtual machining Instruction sets Delay Multicore processing

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Continuous trip count profiling for loop optimization in two-phase dynamic binary translators

Continuous trip count profiling for loop optimization in two...

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annual workshop on interaction between compilers and computer architectures

作者： Youfeng Wu M. Breternitz T. Devor Corporate Technology Group (CTG) Intel Corporation USA Software and Solutions Group (SSG) Intel Corporation USA

Most dynamic binary translators use a two-phase approach to identify and optimize frequently executed code dynamically. In the profiling phase, blocks of code are interpreted or translated without optimization to collect execution frequency information for the blocks. In the optimization phase, frequently executed blocks are grouped into regions and advanced optimizations are applied on them. This approach implicitly assumes that the initial execution of each block is representative of the block throughout its lifetime. In particular, loop optimizations may use the block frequency information to determine loop trip counts to guide their optimizations. If the trip count information is incorrect, however, a loop may be improperly optimized, and program performance suffers. In this paper we show that the initial profile is inadequate at predicting loop trip count information for several integer programs. We propose and evaluate efficient algorithms to continuously profile for trip count. Our results show that accurate trip count information may be obtained with very low overhead (about 0.5%). This enables advanced loop optimizations in dynamic binary translators.

关键词： Frequency Prefetching Magnetohydrodynamic power generation Instruments Pipeline processing Runtime Conferences computer architecture

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Mathematical Foundations of Programming Semantics 1

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丛书名： Lecture Notes in computer Science

1000年

ISBN: (数字)9783540471943

ISBN: (纸本)9783540555117

This volume contains the proceedings of the Seventh International Conferenceon the Mathematical Foundations of Programming Semantics, held at Carnegie Mellon University, March 1991. The conference continued a series of annual meetings, alternating between workshop and conference formats, intended to bring together computer scientists and mathematicians for discussion of research problems, results and directions in programming language semantics and related areas. A major goalof the series is to improve communication and interaction between researchers in these areas and to establish ties between related areas of research. The volume contains revised and refereed versions of each of the contributed papers and refereed papers by three invited speakers:Jon Barwise, John Reynolds, and Mitchell Wand.

关键词： Mathematics of Computing Programming Languages, compilers, Interpreters Computation by Abstract Devices Logics and Meanings of Programs Mathematical Logic and Formal Languages Mathematical Logic and Foundations

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Analysis of path profiling information generated with performance monitoring hardware

Analysis of path profiling information generated with perfor...

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annual workshop on interaction between compilers and computer architectures

作者： A. Shye M. Iyer T. Moseley D. Hodgdon D. Fay Vijay Janapa Reddi D.A. Connor Department of Electrical and Computer Engineering University of Colorado at Boulder USA University of Colorado Boulder Boulder CO US Dept. of Electr. & Comput. Eng. Colorado Univ. Boulder CO USA

Even with the breakthroughs in semiconductor technology that enables billion transistor designs, hardware-based architecture paradigms alone cannot substantially improve processor performance. The challenge in realizing the full potential of these future machines is to find ways to adapt program behavior to application needs and processor resources. As such, run-time optimization has a distinct role in future high performance systems. However, as these systems are dependent on accurate, fine-grain profile information, traditional approaches to collecting profiles at run-time result in significant slowdowns during program execution. A novel approach to low-overhead profiling is to exploit hardware performance monitoring units (PMUs) present in modern microprocessors. The Itanium-2 PMU can periodically sample the last few taken branches in an executing program and this information can be used to recreate partial paths of execution. With compiler-aided analysis, the partial paths can be correlated into full paths. As statistically hot paths are most likely to occur in PMU samples, even infrequent sampling can accurately identify these paths. While traditional path profiling techniques carry a high overhead, a PMU-based path profiler represents an effective lightweight profiling alternative. This paper characterizes the PMU-based path information and demonstrates the construction of such a PMU-based path profiler for a run-time system.

关键词： Information analysis Performance analysis Hardware Runtime Phasor measurement units Instruments computerized monitoring computer architecture Performance gain Counting circuits

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