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共 113 条记录，以下是51-60 订阅

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High performance code generation through lazy activation records 7

High performance code generation through lazy activation rec...

引用

7th workshop on interaction between compilers and computer architectures, INTERACT-7 2003

作者： Satpathy, M. Mahapatrg, R.N. Choudhuri, S. Chitnis, S.V. Applied Software Engineering Group Department of Computer Science University of Reading ReadingRG6 6AY United Kingdom Hardware Software Codesign Group Department of Computer Science Texas AandM University College StationTX77843-5534 United States CMG Wireless Data Solutions B.V. Merweplein 5 Nieuwegein3432 GNß Netherlands

ISBN: (纸本)0769518893

For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to memory spills are much more pronounced in presence of recursion. A function call is usually accompanied by the creation of its activation record at function entry. In this paper, we will deviate from this usual practice;we create an activation record only when we find it necessary. The result is that on many occasions we can execute a function call without actually creating its activation record. We call our strategy lazy activation record strategy (LARS) and show how this strategy is particularly important for call-intensive programs. The LARS subsumes many traditional techniques like leaf-call optimization and tail-recursion optimization, and in addition, it extends Chow's shrink-wrapping in terms of scope and granularity. We also demonstrate how the LARS can be an effective optimization strategy in the case of battery operated embedded systems, since not only can it reduce execution time but also energy consumption. © 2003 IEEE.

关键词： Energy utilization

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An adiabatic framework for a low energy μ-architecture and compiler 7

An adiabatic framework for a low energy μ-architecture and ...

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7th workshop on interaction between compilers and computer architectures, INTERACT-7 2003

作者： Ramarao, Pramod Tyagi, Akhilesh Computer Architecture Lab Department of Electrical and Computer Engineering Iowa State University AmesIA United States

ISBN: (纸本)0769518893

Adiabatic process in thermodynamics transfers energy across zero temperature difference. The adiabatic CMOS design style attempts to switch a transistor to transfer energy across its source and drain while the voltage difference is zero. We define an adiabatic micro-architecture that pushes instructions across zero IPC gradient. The IPC gradient can be zero across time: for the same stage IPC over time does not vary, or across space: adjacent pipeline stages have zero variance. The reason to consider adiabatic micro-architectures is that the energy for a given computation can be shown to be minimum for an adiabatic micro-architecture. An adiabatic compiler, really a back-end, is defined to be a compiler to support an adiabatic micro-architecture achieve its goals. The minimal support provided by an adiabatic compiler includes a static estimation of program ILP. We add new passes to the MachineSUIF compiler, to flag instruction groups that can potentially walk through a superscalar pipeline as a group. Hence, these instruction groups offer a fairly robust model of superscalar microarchitecture ILP. A compile time scheduling analysis can also generate instruction slack values. The slack indicates the program region within which an instruction can be scheduled. We also present a dispatch stage dynamic scheduling algorithm that utilizes the compiler annotated slacks to reschedule instructions with the explicit objective of minimizing the dispatch stage IPC variance. In other words, the proposed dispatch stage is adiabatic. Preliminary experimental results demonstrate an average reduction of 4.16% in IPC variance over SPEC2000 benchmarks with the adiabatic compiler and microarchitecture. The preliminary evaluation also shows the average processor dispatch stage energy reduction of 3.9% over the same SPEC2000 benchmarks. We expect to add similar IPC smoothening control knobs at instruction fetch and issue stages as well in the future, which should result in a more signifi

关键词： computer architecture

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Code size and performance optimization for mobile JavaScript just-in-time compiler

Code size and performance optimization for mobile JavaScript...

引用

2010 workshop on interaction between compilers and computer Architecture, INTERACT-14

作者： Lee, Seong-Won Moon, Soo-Mook Jung, Won-Ki Oh, Jin-Seok Oh, Hyeong-Seok School of Electrical Engineering and Computer Science Seoul National University Seoul 151-742 Korea Republic of

ISBN: (纸本)9781605589213

Full web browsing with smart phones requires a high-performance JavaScript engine since JavaScript execution with a mobile CPU is slow. So, mobile JavaScript engines employ a just-in-time compiler (JITC), which translates JavaScript code to machine code at runtime. One issue is that since mobile phones suffer from tight memory constraints, the JITC needs to keep a low memory footprint by generating small-sized machine code. In fact, many mobile CPUs support half-sized encoding for small code size with small performance degradation, as in the ARM Thumb2. This paper describes our code generation and optimization for a mobile JavaScript JITC in the Webkit's SquirrelFish Extreme (SFX) for the ARM Thumb2. We try to generate as many 16-bit instructions as possible and reduce the data area, while strictly following the code generation guidelines of the SFX, which actually leaves little room for code optimization. Our experimental results show that we could reduce the code size by 29% with a performance degradation of 3.5%, compared to the ARM version of the SFX. Copyright © 2010 ACM.

关键词： Engines

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Code cache management schemes for dynamic optimizers

Code cache management schemes for dynamic optimizers

引用

annual workshop on interaction between compilers and computer architectures

作者： K. Hazelwood M.D. Smith Division of Engineering and Applied Sciences Harvard University USA

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RaPTEX: A resource-focused toolchain for rapid prototyping of embedded communication systems

RaPTEX: A resource-focused toolchain for rapid prototyping o...

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2010 workshop on interaction between compilers and computer Architecture, INTERACT-14

作者： Peng, Shaolin Parsons, Gregory Dean, Alexander G. Center for Efficient Scalable and Reliable Computing Department of Electrical and Computer Engineering North Carolina State University Raleigh NC 27695-7256 United States

ISBN: (纸本)9781605589213

This paper introduces the RaPTEX toolchain and its use for rapid prototyping and evaluation of embedded communication systems. This toolchain is unique for several reasons. First, by using static code analysis techniques, it is able to predict both the typical case and bounds for resource usage, such as computational, memory (both static and dynamic), and energy requirements. Typical software toolchains report only on partial memory requirements (only code and static data, but not stack memory) and ignore other the important resources. Second, it provides a graphical user interface with configurable software building blocks which allows easy creation and customization of protocol stacks. Third, it targets low-cost, low-energy hardware, allowing the creation of low-cost systems. We demonstrate the RaPTEX toolchain by evaluating different design options for an experimental ultrasonic communication system for biotelemetry in extremely shallow waters. The power, size, mass and cost constraints of this application make it critical to pack as much processing into the available resources as possible. The RaPTEX toolchain analyzes resource use, enabling the system to run safely closer to the edge of the resource envelope. The toolchain also helps users with the rapid prototyping of communication protocols for embedded systems by providing users with quick feedback on resource requirements. We demonstrate the use and output of the toolchain. We compare the accuracy of its predictions against measurements of actual execution of the actual underwater communication system on real hardware. Copyright 2010 ACM.

关键词： Graphical user interfaces

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Performance characterization of data mining benchmarks

Performance characterization of data mining benchmarks

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2010 workshop on interaction between compilers and computer Architecture, INTERACT-14

作者： Mekkat, Vineeth Natarajan, Ragavendra Hsu, Wei-Chung Zhai, Antonia Department of Computer Science and Engineering University of Minnesota - Twin Cities Minneapolis MN 55455 United States Department of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781605589213

Explosive growth in the availability of various kinds of data in both commercial and scientific domains have resulted in an unprecedented need to develop novel data-driven, knowledge discovery techniques. Data mining is one such data-centric application. It consists of methods to discover interesting, nontrivial, and useful patterns hidden within massive amounts of data. Researchers from both academia and industry have recognized that the challenges of data mining applications will help shape the future of multi-core processor and parallelizing compiler designs. However, relatively little has been done to understand the performance characteristics of these applications on modern multi-core processors. The exponential growth of on-chip resources make it critical to exploit parallelism at all granularities for improving the performance of data mining applications. In this paper, we examine the instruction-level, memory-level and thread-level parallelism available in data mining applications. We observe that (i) data mining applications have a slightly different instruction mix from SPEC integer applications, and this difference can potentially lead to different ILP extraction;ii) although many data mining applications suffer from data cache miss penalty, similar to SPEC integer applications, different techniques must be developed to enable effective prefetching due to the existance of complex and irregular data structures, such as hash tables;(iii) although data mining applications have large amount of thread-level parallelism, efficient extraction of such parallelism depends on on-chip cache performance;and (iv) the performance characteristics of data mining applications can vary at runtime, and thus techniques that dynamically tune the applications to adapt to such variations are desired. Copyright 2010 ACM.

关键词： Extraction

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Code size efficiency in global scheduling for ILP processors

Code size efficiency in global scheduling for ILP processors

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annual workshop on interaction between compilers and computer architectures

作者： Huiyang Zhou T.M. Conte Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University USA

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Message From The Program Chair

Message From The Program Chair

引用

annual workshop on interaction between compilers and computer architectures

作者： Wei C. Hsu Department of Computer Science and Technology Tsinghua National Laboratory for Information Science and Technology Beijing China

We received a total of 25 submissions for INTERACT-8. Each member of the Program Committee was asked to evaluate and rank the papers based on his areas of expertise and interests. The paper reviews were done during December 2003. With the semester ending and the holidays coming, it was rather hectic for all committee members. I would like to express my appreciation and thank all the Program Committee members and external referees for their efforts and timely reviews. The annual workshop on interaction between compilers and computer architectures (INTERACT) has been organized to promote new ideas and to present recent research and developments in compiler and architecture/micro-architecture techniques that enhance each other’s capabilities and performance. We are very pleased to include 12 papers in the final workshop program. We hope the program will generate excitement and research interest among the workshop participants, and this proceedings will further research and developments in the interaction between compilers and computer architectures. The INTERACT workshop has entered its eighth year. I would like to thank all the contributors and participants, whose interest and support are the basis for the existence of this workshop. Special thanks are due to Antonio Gonzales and Eric Rotenberg, who have served on the Program Committee for the last five years. As the Program Chair I am truly impressed by their dedication. I would also like to thank the general chair, Gyungho Lee, for continuously securing the necessary funding to print the workshop proceedings.

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A preliminary study on data allocation of on-chip dual memory banks

A preliminary study on data allocation of on-chip dual memor...

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annual workshop on interaction between compilers and computer architectures

作者： Jeonghun Cho Jinhwan Kim Yunheung Paek Department of Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology South Korea

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computer Architecture 2012

引用

丛书名： Lecture Notes in computer Science

2012年

作者： Ana Lucia Varbanescu Anca Molnos Rob van Nieuwpoort

ISBN: (数字)9783642243226

ISBN: (纸本)9783642243219

This book constitutes the thoroughly refereed post-conference proceedings of the workshops held at the 37th International Symposium on computer Architecture, ISCA 2010, in Saint-Malo, France, in June 2010. The 28 revised full papers presented were carefully reviewed and selected from the lectures given at 5 of these workshops. The papers address topics ranging from novel memory architectures to emerging application design and performance analysis and encompassed the following workshops: A4MMC, applications for multi- and many-cores; AMAS-BT, 3rd workshop on architectural and micro-architectural support for binary translation; EAMA, the 3rd workshop for emerging applications and many-core architectures; WEED, 2nd workshop on energy efficient design, as well as WIOSCA, the annual workshop on the interaction between operating systems and computer architecture.

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