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An empirical study of data speculation use on the Intel Itanium 2 processor

An empirical study of data speculation use on the Intel Itan...

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annual workshop on interaction between compilers and computer architectures

作者： M. Mock R. Villamarin J. Baiocchi Department of Computer Science University of Pittsburgh Pittsburgh PA USA

The Intel Itanium architecture uses a dedicated 32-entry hardware table, the advanced load address table (ALAT) to support data speculation via an instruction set interface. This study presents an empirical evaluation of the use of the ALAT and data speculative instructions for several optimizing compilers. We determined what and how often compilers generated the different speculative instructions, and used the Itanium's hardware performance counters to evaluate their run-time behavior. We also performed a limit study by modifying one compiler to always generate data speculation when possible. We found that this aggressive approach significantly increased the amount of data speculation and often resulted in performance improvements, of as much as 10% in one case. Since it worsened performance only for one application and then only for some inputs, we conclude that more aggressive data speculation heuristics than those employed by current compilers are desirable and may further improve performance gains from data speculation.

关键词： computer architecture Hardware computer aided instruction computer science Optimizing compilers Counting circuits Runtime Application software Performance gain Concurrent computing

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Automatic low overhead program instrumentation with the LOPI framework

Automatic low overhead program instrumentation with the LOPI...

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annual workshop on interaction between compilers and computer architectures

作者： S. Kaagstrom H. Grahn L. Lundberg Dept. of Syst. & Software Eng. Blekinge Inst. of Technol. Ronneby Sweden Department of Systems and Software Engineering Blekinge Institute of Technology Ronneby Sweden

Program instrumentation is an important technique for different tasks such as performance measurements, debugging, and coverage analysis. Instrumentation, however, poses two important requirements to be useful: it must be easy to apply and it should perturb the application as little as possible. In this paper, we present the LOPI framework, which provides a simple means to automatically instrument binary files with low perturbation. An evaluation of the LOPI framework with detailed measurements of seven SPEC CPU2000 benchmarks show that the it gives lower perturbation in terms of instructions executed and cache behavior than Dyninst. For example, a LOPI instrumented application executes on average 36% more instructions, while a Dyninst instrumented application executes 49% more instructions for a common performance-oriented instrumentation, than the uninstrumented application.

关键词： Instruments Measurement Performance analysis Debugging Program processors Optimizing compilers computer architecture Software engineering Security High level languages

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Improving Low Power Processor Efficiency with Static Pipelining

Improving Low Power Processor Efficiency with Static Pipelin...

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annual workshop on interaction between compilers and computer architectures

作者： Ian Finlayson Gang-Ryung Uh David Whalley Gary Tyson Department of Computer Science Florida State University USA Department of Computer Science Boise State University USA

A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. In this paper, we propose to respond to these conflicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefits of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can significantly reduce power consumption without adversely affecting performance.

关键词： Registers Pipeline processing Optimization Radio frequency Clocks Hazards Energy consumption

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Compiler analysis for trace-level speculative multithreaded architectures

Compiler analysis for trace-level speculative multithreaded ...

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annual workshop on interaction between compilers and computer architectures

作者： C. Molina A. Gonzalez J. Tubella Department Engineering Infomàtica i Matemàtiques Universitat Rovira i Virgili Tarragona Spain Department dArquitectura de Computadors Universitat Poliltècnica de Catalunya Barcelona Spain

Trace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating on the result of several traces. The other thread executes speculated traces and verifies the speculation made by the first thread. In this paper, we propose a static program analysis for identifying candidate traces to be speculated. This approach identifies large regions of code whose live-output values may be successfully predicted. We present several heuristics to determine the best opportunities for dynamic speculation, based on compiler analysis and program profiling information. Simulation results show that the proposed trace recognition techniques achieve on average a speed-up close to 38% for a collection of SPEC2000 benchmarks.

关键词： Microarchitecture Data structures computer architecture Frequency Buildings Performance analysis Runtime Flow graphs Testing Information analysis

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Exploitation of instruction-level parallelism for optimal loop scheduling

Exploitation of instruction-level parallelism for optimal lo...

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annual workshop on interaction between compilers and computer architectures

作者： J. Muller D. Fimmel R. Merker Department of Electrical Engineering Dresden University of Technology Dresden Germany

We present a loop scheduling approach which optimally exploits instruction-level parallelism. We develop a flow graph model for the resource constraints allowing a more efficient implementation. The method supports heterogeneous processor architectures and pipelines functional units. Our linear programming implementation produces an optimum loop schedule, making the technique applicable to production compilation and hardware parametrization. Compared to earlier approaches, the approach can provide faster loop schedules and a significant reduction of the problem complexity and solution time.

关键词： Flow graphs Resource management Processor scheduling Conferences computer architecture Digital filters Parallel processing Adders Bars Decision support systems

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The effect of compiler optimizations on Pentium 4 power consumption

The effect of compiler optimizations on Pentium 4 power cons...

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annual workshop on interaction between compilers and computer architectures

作者： J.S. Seng D.M. Tullsen Department of Computer Science and Engineering University of California La Jolla CA USA

This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of general optimization and specific optimization. We classify general optimizations as those compiler flags which enable a set of compiler optimizations. Specific optimizations are those which can be enabled and disabled individually. The three specific optimizations we study are loop unrolling, loop vectorization, and function inlining. The binaries used in this study are generated using the Intel C++ compiler, which allows fine-grained control over each of these specific optimizations.

关键词： Optimizing compilers Energy consumption Computational modeling computer architecture Clocks Power measurement computer science Power engineering and energy Microprocessors Circuits

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Exploiting procedure level locality to reduce instruction cache misses

Exploiting procedure level locality to reduce instruction ca...

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annual workshop on interaction between compilers and computer architectures

作者： R.V. Batchu D.A. Jimenez Department of Computer Science Rutgers University USA

High instruction fetch bandwidth is essential for high performance in today's wide-issue out-of-order processors. Instruction caches must provide a low miss rate as well as low latency. We introduce procedure level relocation, a class of dynamic feedback-directed optimizations that substantially reduce the instruction cache miss rate by exploiting the temporal locality of procedure usage. Based on the observation that half of all procedures executed are at most 128 bytes in length, we present a small procedure cache, a small and fast explicitly managed memory for storing small procedures. We show that procedure level relocation into a small procedure cache reduces the instruction cache miss rate by an average of 15%.

关键词： Memory management Bandwidth Delay Hardware computer science Out of order High level languages Computational modeling Frequency Conferences

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Procedure cloning and integration for converting parallelism from coarse to fine grain

Procedure cloning and integration for converting parallelism...

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annual workshop on interaction between compilers and computer architectures

作者： Won So A. Dean Department of Electrical and Computer Engineering NC State University Raleigh NC USA

This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods extend whole-program optimization by expanding the scope of the compiler through a combination of software thread integration and procedure cloning. In each experiment we integrate a frequently executed procedure with itself twice or thrice, creating two clones. Then, based on profile data we select at compile time the fastest version (original or clone) and modify call sites as needed. We demonstrate our technique by cloning and integrating three procedures from cjpeg and djpeg at the C source code level, compiling with four compilers for the Itanium EPIC architecture and measuring the performance with the on-chip performance measurement units. For cjpeg, which is not significantly constrained by the i-cache, we find integration consistently improves code generated by all compilers but one, with a mean program speedup of 11.99%.

关键词： Cloning Yarn Embedded system Data analysis Parallel processing Program processors Runtime Application software Optimizing compilers Measurement

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Data movement optimization for software-controlled on-chip memory

Data movement optimization for software-controlled on-chip m...

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annual workshop on interaction between compilers and computer architectures

作者： M. Fujita M. Kondo H. Nakamura Research Center for Advanced Science and Technology University of Tokyo Meguro Tokyo Japan Japan Science and Technology Agency Kawaguchi Saitama Japan

In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip memories to achieve higher performance by utilizing on-chip memory. Because such properties are automatically controlled by hardware in conventional caches, a cost of optimization for a program becomes a matter that should be considered. In this paper, we propose an data movement optimization technique for software-controlled on-chip memory. We evaluated the proposed method using two applications. The results reveal that the proposed technique can drastically reduce memory stall cycles and achieve high performance.

关键词： computer architecture Random access memory Software performance Automatic control Bandwidth Optimizing compilers Degradation Hardware Delay System-on-a-chip

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Link-time optimization techniques for eliminating conditional branch redundancies

Link-time optimization techniques for eliminating conditiona...

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annual workshop on interaction between compilers and computer architectures

作者： M. Fernandez R. Espasa Computer Architecture Department Universitat Poliltècnica de Catalunya Barcelona Spain

Optimizations performed at link time or directly applied to final program executables have received increased attention in recent years. This work discusses the discovery and elimination of redundant conditional branches in the context of a link-time optimizer, an optimization that we call conditional branch redundancy elimination (CBRE). Our experiments show that around 20% of conditional branches in a program can be considered redundant because their outcomes can be determined from a previous short dynamic execution frame. Then, we present several CBRE algorithms targeted at optimizing away these redundancies. Our results show that around 5% of the conditional branch redundancy detected can indeed be eliminated, which translates into execution time reductions of around 4%. We also give accurate measures of the impact of applying CBRE in code growth.

关键词： computer architecture Performance evaluation Instruments Electronic mail Time measurement Program processors Optimizing compilers Performance analysis Production Force feedback

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