The electronic nose (eNose) is applied to detect, monitor and identify a wide range of environmental organic, inorganic and biochemical vapors. Typically, airborne substances are made up of hundreds of different inorg...
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The electronic nose (eNose) is applied to detect, monitor and identify a wide range of environmental organic, inorganic and biochemical vapors. Typically, airborne substances are made up of hundreds of different inorganic/organic or bio molecules. The molecules usually have properties that can be identified with different detection systems, such as gas chromatography and mass spectrometry. However, the systems are usually bulky, expensive and time consuming to be deployed portably. Recently, the growing application of polymorphous computing opened up the opportunity for the use of neural net and genetic algorithm development for electronic nose selectivity with critical information extraction methodology done in real-time. The additional use of Power Aware computing (PAC) and Polymorphous computing Architecture (PCA) enables the eNose to "Tailor" power through energy management at all levels of application/system for size, weight, power, scalability, complexity and temporal and functional reconfiguration constraints.
Recently, graphics hardware architectures have begun to emphasize versatility, offering rich new ways to programmatically reconfigure the graphics pipeline. In this paper we explore whether current graphics architectu...
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ISBN:
(纸本)0769518591
Recently, graphics hardware architectures have begun to emphasize versatility, offering rich new ways to programmatically reconfigure the graphics pipeline. In this paper we explore whether current graphics architectures can be applied to problems where general-purpose vector processors might traditionally be used We develop a programming framework and apply it to a variety of problems, including matrix multiplication and 3-SAT Comparing the speed of our graphics card implementations to standard CPU implementations, we demonstrate startling performance improvements in many cases, as well as room for improvement in others. We analyze the bottlenecks and propose minor extensions to current graphics architectures which would improve their effectiveness for solving general-purpose problems. Based on our results and current trends in microarchitecture, we believe that efficient use of graphics hardware will become increasingly important to high-performance computing on commodity hardware.
In this paper we present an approach to minimize the power consumption in logic synthesis stage by using the gate decomposition technique. Owing to the power consumption of ICs is not only decided by the switching, ac...
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ISBN:
(纸本)0769515614;0769515622
In this paper we present an approach to minimize the power consumption in logic synthesis stage by using the gate decomposition technique. Owing to the power consumption of ICs is not only decided by the switching, activity of each gate but also depended on the, the target library, the major difference between our algorithm and the traditional methods is that we consider the power consumption of gate with different type. Besides, by the usage of inverter relocation based on the Demorgan's law we can further reduce the IC's total power consumption, Under the cases of different probabilities of input signals switching rate are applied, experimental results show that our approach can further reduce tip to 12.7% average power consumption than the case applied ExDecomp/HeuDecomp algorithm[14].
Checkpointing protocols for distributed computing systems can also be applied to mobile computing systems, but the unique characteristics of the mobile environment need to be taken into account. In this paper, an impr...
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In this paper we consider the fair flow problem in multiple source multiple sink network, as applied to telecommunication networks. We present an iterative algorithm for computing fair routing in networks where the av...
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ISBN:
(纸本)0769516718
In this paper we consider the fair flow problem in multiple source multiple sink network, as applied to telecommunication networks. We present an iterative algorithm for computing fair routing in networks where the available resources are shared among competing flows according to a max-min fair sharing criterion. Our main objective is computing optimal routing paths, with regard to max-min fairness, in stable and known traffic conditions. It is a linear programming based approach which permits a lexicographical maximization of the vector of fair-share attributed to the connections competing for network resources. An optimality proof and some computational results are also presented.
Direct Combination (DC) is a recently introduced user interaction principle. The principle (previously applied to desktop computing) can greatly reduce the degree of search, time, and attention required to operate use...
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Eddy current techniques (ECT) for Nondestructive Testing and Evaluation (NDT/NDE) of conducting materials is one of the most application-oriented field of research within electromagnetics. In this work, a fuzzy approa...
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Eddy current techniques (ECT) for Nondestructive Testing and Evaluation (NDT/NDE) of conducting materials is one of the most application-oriented field of research within electromagnetics. In this work, a fuzzy approach is proposed to estimate the presence of holes in metallic plates starting from a set of experimental eddy current measurements, carried out at the NDT Lab in Reggio Calabria. The above inverse problem is solved by means of a system that extracts information on the specimen under test from the measurements and implements a priori constraints to facilitate the detection and characterization of the defect. The method utilizes the concepts of fuzzy inference in order to estimate the location of the defect from a reduced set of features.
I-DDQ testing has become a widely accepted defect detection technique in CMOS ICs. However its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a ...
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ISBN:
(纸本)0769515614;0769515622
I-DDQ testing has become a widely accepted defect detection technique in CMOS ICs. However its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new I-DDQ testing scheme is proposed. This scheme is based on the elimination, during I-DDQ testing, of the normal leakage current from the sensing node of the circuit under test so that already known in the open literature I-DDQ sensing techniques can be applied in deep submicron.
Mobile computing is becoming increasingly important due to the rise in the number of portable computers and the desire to have continuous network connectivity to the Internet irrespective of the physical location of t...
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Mobile computing is becoming increasingly important due to the rise in the number of portable computers and the desire to have continuous network connectivity to the Internet irrespective of the physical location of the node. Mobile IP, the more popular global mobility solution, was designed to support mobility of a single host. Even though the same protocol can be applied in the case of network mobility providing connectivity to mobile networks introduces many issues related to the scalability, security and QoS. Instead, a mobile network can be cited as a remote site, trying to establish secured communication with the home network. This view of mobile network solves many issues related to QoS, security and scalability. The objective of this paper is to explore the possibility of using different VPN techniques to provide connectivity for mobile network and measure the corresponding end-to-end performance of real time traffic and best effort traffic patterns.
A novel method focused on the symbolic computation of Noise Figure (NF) for MOS Transistor (MOST) circuits, is presented. In order to improve the computation time, a pure-nodal-analysis (PNA) method is applied by mode...
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A novel method focused on the symbolic computation of Noise Figure (NF) for MOS Transistor (MOST) circuits, is presented. In order to improve the computation time, a pure-nodal-analysis (PNA) method is applied by modeling all the circuit elements using the nullor. To demonstrate the suitability of the proposed method, two illustrative examples are given, where the NF computed using the proposed method, is compared with the simulation results using HSPICE.
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