imageprocessing.and image analysis tasks have large data processing.requirements and inherent parallelism and are well suited to implementation on digital optical processors because of the parallelism and free interc...
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ISBN:
(纸本)0936659661
imageprocessing.and image analysis tasks have large data processing.requirements and inherent parallelism and are well suited to implementation on digital optical processors because of the parallelism and free interconnection capabilities of optical systems. Recently, several techniques for constructing optical cellular logic processors for imageprocessing.have been proposed. Through parallel studies of architectures, algorithms, mathematical structures, and optics we have found that: 1) cellular automata are appropriate models for parallel imageprocessing.machines;2) an image algebra extending from mathematical morphology can lead to a formal parallel language approach to the design of imageprocessing.algorithms;3) the algebraic structure serves as a framework for both algorithms and architectures of parallel imageprocessing.and 4) optical computing techniques are able to implement image algebra based on cellular logic architecture. We discuss image algebra and architectures for its implementation.
This conference proceedings contains 20 articles on current developments in the field of imageprocessing. Among the topics covered are: Data compression;digital signal processing.Freeze-flame coder;algorithms and ana...
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ISBN:
(纸本)0892527927
This conference proceedings contains 20 articles on current developments in the field of imageprocessing. Among the topics covered are: Data compression;digital signal processing.Freeze-flame coder;algorithms and analysis;Rotated images registration;Adaptive processing.techniques;digital photogrammetry;Memory management;Multiwindow displays;and Halftone imageprocessing.
Custom VLSI circuits that perform real-time Radon transformations of image data in a parallel pipelined architecture are presented. They will allow real-time operation of projection-based algorithms by reducing image ...
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ISBN:
(纸本)0818608048
Custom VLSI circuits that perform real-time Radon transformations of image data in a parallel pipelined architecture are presented. They will allow real-time operation of projection-based algorithms by reducing image data bandwidth sufficiently for commercially available DSP (digital signal-processing. ICs.
The architecture used in a 16-pin CMOS VLSI digital signal processor (DSP) that was designed by the authors to perform both ANSI and CCITT versions of the adaptive digital pulse code modulation standard is described. ...
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The architecture used in a 16-pin CMOS VLSI digital signal processor (DSP) that was designed by the authors to perform both ANSI and CCITT versions of the adaptive digital pulse code modulation standard is described. The part is designed to run from a 20-MHz clock source with an instruction cycle time of 100 ns. This design is a good example of the power of application-specific DSP designs to reduce the cost of implementing stable algorithms.
ZSA, an industrial imageprocessing.system is characterized by a modern parallel architecture for digital signal processing. Besides the use of standard video cameras the system is strongly intended to be used with on...
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Two sets of one-dimensional (1-D) FIR digital filtering architectures are proposed to reduce computational complexity and to increase throughput rate. Each architecture is regular in structure with a high degree of pa...
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Two sets of one-dimensional (1-D) FIR digital filtering architectures are proposed to reduce computational complexity and to increase throughput rate. Each architecture is regular in structure with a high degree of parallelism and pipelining. Consequently, they are suitable for VLSI or multiprocessor implementation. Infinite linear convolution is first converted into finite length linear or cyclic convolution in a polynomial ring. Certain algorithms that are used to reduce computational complexity in finite length linear or cyclic convolution can then be applied to reduce computational complexity of polynomial convolution and give the resulting filter structure.
The authors investigate a recently developed modular recursive estimation (MRE) algorithm using discrete-event models (DEM). A concurrent, pipelined adaptive-signal-processing.architecture based on parallel networking...
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The authors investigate a recently developed modular recursive estimation (MRE) algorithm using discrete-event models (DEM). A concurrent, pipelined adaptive-signal-processing.architecture based on parallel networking of these MREs is proposed. The main feature of the MRE is a discerning update strategy for parameter estimates, in contrast to the continual update strategy of conventional algorithms. This discerning update strategy not only results in a higher degree of modularity, but also facilitates more effective use of data information.
The medial axis transform represents a region of a digitalimage as the union of maximal upright squares contained in the region. The authors present algorithms to compute the perimeter and area of the region covered ...
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ISBN:
(纸本)0818608048
The medial axis transform represents a region of a digitalimage as the union of maximal upright squares contained in the region. The authors present algorithms to compute the perimeter and area of the region covered by a set of n upright rectangles in O(log n log log n) time using O(n) processors for the shared memory model. The result is faster than previous results and is optimal within an O(log log n) factor. The authors compute the contour of the digitalimage in optimal time and show how to obtain the medial axis transform, given an array representation.
Efficient parallel algorithms for implementation on a VLSI array are derived for several signal-processing.tasks. The parallel architecture has n**2 memory modules storing the input data, which is accessed by n PEs (p...
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ISBN:
(纸本)0271006080
Efficient parallel algorithms for implementation on a VLSI array are derived for several signal-processing.tasks. The parallel architecture has n**2 memory modules storing the input data, which is accessed by n PEs (processing.elements). Several signal-processing.tasks such as k selection, median filtering, labeling a 0/1 image, etc. , are considered. For all the problems, linear speedup is obtained. For the k selection problem, an efficient parallel solution is provided using log transformation on the data. The expected time of this method is O(n) with a small constant factor. The array is suitable for general-purpose signal processing.and can be implemented using a limited chip set.
An integrated digital signal processing.(DSP) machine will accept data from a plethora of sensors and/or subsystems which may be running at different speeds and with different precision/dynamic range metrics. Data wou...
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An integrated digital signal processing.(DSP) machine will accept data from a plethora of sensors and/or subsystems which may be running at different speeds and with different precision/dynamic range metrics. Data would be manipulated using a set of algorithms which perform a variety of filtering or transform tasks. The design of such a machine that is considered integrates recent advancements in mesh-array synthesis with processor technology. The result is a high-throughput GIPS-class DSP machine capable of responding to a wide mix of system- and user-defined DSP problems.
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