In this paper, we consider a generalized broadcasting feature for mesh connected computers (MCCs) which consists of N = N 1 2 × N 1 2 processors with broadcasting features in each row and each column. This multip...
详细信息
In this paper, we consider a generalized broadcasting feature for mesh connected computers (MCCs) which consists of N = N 1 2 × N 1 2 processors with broadcasting features in each row and each column. This multiple broadcast allows parallel data transfers within rows and columns of processors. The proposed architecture is well suited for solution of problems in linear algebra, imageprocessing. computational geometry, and numerical computations. We develop parallel algorithms for many problems in these areas: for example, we can find max in O(N 1 6 ) , median in O(N 1 6 ( log N) 2 3 ) , convex polygon of a digitized picture in O(N 1 6 ) , and nearest neighbor in O(N 1 6 ) , while these problems need Ω(N 1 3 ) on a 2-MCC with single broadcast. We also derive bounds on the speedups obtainable with broadcasting.
A commercially available system is described that can connect to virtually any sensor, acquire images at virtually any resolution, and process sensor data at very high speeds. The system is able to acquire the output ...
详细信息
A commercially available system is described that can connect to virtually any sensor, acquire images at virtually any resolution, and process sensor data at very high speeds. The system is able to acquire the output of sensors such as line scan devices (CCD laser, diode), area scan devices (CCD, vidicon, scanning electron beam), analog signals, digital signals, etc. The advantages of processing.and communicating variable-resolution images at a fixed data rate are discussed. Variable resolution imageprocessing.can concentrate hardware processing.resources on regions of interest within a larger image. Previously, these functions were implemented with unique hardware designed for each particular task. This system is configured at the software and systems integration levels, rather than at the hardware design level. Also, this modular family uses the MAX-bus for image transfers, allowing it to interface with a large body of available imageprocessing.hardware.
This paper describes a reconfigurable imageprocessing.system, IDATEN, that can process time varying images at video rate. A reconfigurable pipeline architecture is presented as system architecture. In this architectu...
详细信息
This paper describes a reconfigurable imageprocessing.system, IDATEN, that can process time varying images at video rate. A reconfigurable pipeline architecture is presented as system architecture. In this architecture, multiple processing.modules are interconnected via a network. Each processing.module can execute the basic functions for imageprocessing.at video rate. The network is based on a Benes multistage switching network, and its configuration is extended such that multiple branching is supported for imageprocessing. The prototype system IDATEN was constructed to verify the validity of the relevant architecture, and several imageprocessing.algorithms were implemented and tested.
A description is given of the HMESH architecture, a modified broadcast-bus VLSI architecture consisting of an N multiplied by N mesh connected structure and a hierarchy of broadcast buses in each row and in each colum...
详细信息
ISBN:
(纸本)0818608048
A description is given of the HMESH architecture, a modified broadcast-bus VLSI architecture consisting of an N multiplied by N mesh connected structure and a hierarchy of broadcast buses in each row and in each column such that every bus has k processing.elements (PEs). That is, in any row or column, in the first level there are N/k buses with groups of k PEs connected to each bus. One PE from each of these groups is connected to second level of buses in a similar manner. This is recursively done until there are k PEs left, connected by a broadcast bus. With this architecture the authors show that many problems with applications to imageprocessing.and pattern analysis can be solved in O(log N) time.
A real-time architecture for the corner-turn transposition algorithm is proposed that uses the inherent parallelism and pipelining of the algorithm. A fundamental cell is defined that represents a matrix element and i...
详细信息
A real-time architecture for the corner-turn transposition algorithm is proposed that uses the inherent parallelism and pipelining of the algorithm. A fundamental cell is defined that represents a matrix element and is capable of handling data B bits in width. The cells are connected in a pipelined fashion along the rows (columns) of the matrix with interconnection between adjacent rows (columns) in a serpentine organization. The architecture is simple in structure and has local interconnection of the elements, which eliminates communication problems and achieves a high throughput as I/O transfers are eliminated. It is easily implementable in VLSI and has a minimum pin-out (2B plus 4 pins). It has a commendable cost/performance ratio and has wide applications in real-time imageprocessing.
Component labelling is an important part of region analysis in imageprocessing. Component labelling consists of assigning labels to pixels in the image such that adjacent pixels are given the same labels. There are v...
详细信息
Component labelling is an important part of region analysis in imageprocessing. Component labelling consists of assigning labels to pixels in the image such that adjacent pixels are given the same labels. There are various approaches to component labelling. Some require random access to the processed image; some assume special structure of the image such as a quad tree. algorithms based on sequential scan of the image are attractive to hardware implementation. One method of labelling is based on a fixed size local window which includes the previous line. Due to the fixed size window and the sequential fashion of the labelling process, different branches of the same object may be given different labels and later found to be connected to each other. These labels are con-sidered to be equivalent and must later be collected to correctly represent one single object. This approach can be found in [F,FE,R]. Assume an input binary image of size NxM. Using these labelling algorithms, the number of equivalent pair generated is bounded by O(N*M). The number of distinct labels is also bounded by O(N*M). There is no known algorithm that merge the equivalent label pairs in time linear to the number of pairs, that is in time bounded by O(N*M). We propose a new labelling algorithm which interleaves the labelling with the merging process. The labelling and the merging are combined in one algorithm. Merged label information is kept in an equivalent table which is used to guide the labelling. In general , the algorithm produces fewer equivalent label pairs. The combined labelling and merging algorithm is O(N*M), where NxM is the size of the image. Section II describes the algorithm. Section III gives some examples We discuss implementation issues in section IV and further discussion and conclusion are given in Section V.
The following topics are dealt with: cellular arrays for signal processing.high-speed signal processing.multidimensional digital signal processing.(DSP);beamforming and array processing.computer memories and data stor...
详细信息
ISBN:
(纸本)0818608161
The following topics are dealt with: cellular arrays for signal processing.high-speed signal processing.multidimensional digital signal processing.(DSP);beamforming and array processing.computer memories and data storage;structures for DSP;radar signal processing.adaptive signal processing.robotics;computer networks;learning machines;arithmetic for DSP;military applications of signal processing.imageprocessing.signal processing.algorithms;control applications;array and parallel processing.signal restoration and error detection;algorithms and architecture;pattern recognition;spectral analysis and modeling;control design;and VLSI for DSP. Abstracts of individual papers can be found under the relevant classification codes in this or other issues.
The feasibility of a proposed star field image pattern recognition system has been demonstrated by developing and demonstrating the major portions of the software which are required. This system includes an image samp...
The feasibility of a proposed star field image pattern recognition system has been demonstrated by developing and demonstrating the major portions of the software which are required. This system includes an image sampling device which transforms the visual image into a form suitable for computer digitalimageprocessing. The algorithms developed for this study are capable of processing.the image in this form to extract star locations and relative brightnesses, and to perform pattern recognition in order to identify the viewed star field from a reduced master chart of the area.
Computer recognition and inspection of objects is, in general , a complex procedure requiring a variety of kinds of steps which successively transform the iconic data to recognition information. We hypothesize that th...
详细信息
Computer recognition and inspection of objects is, in general , a complex procedure requiring a variety of kinds of steps which successively transform the iconic data to recognition information. We hypothesize that the difficulty of today's computer vision and recognition technology to be able to handle unconstrained environments is due to the fact that the existing algorithms are specialized and do not develop one or more of the necessary steps to a high enough degree. Our thesis is that there are no shortcuts. A recognition methodology must pay substantial attention to each of the following five steps: conditioning, labeling, grouping, extracting, and matching.
We present a two-dimensional cellular hypercube architecture for imageprocessing.that combines features of the conventional hypercube and cellular logic architectures for 2-D computation cells. A unified theory of pa...
详细信息
We present a two-dimensional cellular hypercube architecture for imageprocessing.that combines features of the conventional hypercube and cellular logic architectures for 2-D computation cells. A unified theory of parallel binary imageprocessing. binary image algebra (BIA), serves as a software tool for designing parallel imageprocessing.algorithms. To match the hardware to the software, we characterize the cellular processors using the same algebraic structure as BIA. The two-dimensional cellular (hypercube image processor is a cellular SIMD machine with N2 cells and has a simple overall organization, low cell complexity and fast processing.ability. An optical cellular hypercube implementation of BIA is proposed which offers parallel input/output and global interconnection capabilities which are difficult to do in planar VLSI technology.
暂无评论