This conference proceedings contains 41 papers and consisted of six separate sessions: image Compression, Instrumentation, Theoretical Concepts, algorithms, Registration and Modeling, and Restoration and Enhancement. ...
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ISBN:
(纸本)0892527323
This conference proceedings contains 41 papers and consisted of six separate sessions: image Compression, Instrumentation, Theoretical Concepts, algorithms, Registration and Modeling, and Restoration and Enhancement. The papers dealt with various respects of optical imageprocessing. including image encoding, enhancement, analysis, restoration, and reconstruction Many presented algorithms for imageprocessing.
The author discusses the design of VLSI imageprocessing.arrays, covering algorithm analysis, architecture, and technology. Several popular array architectures are presented which exploit the massive computing capabil...
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The author discusses the design of VLSI imageprocessing.arrays, covering algorithm analysis, architecture, and technology. Several popular array architectures are presented which exploit the massive computing capability offered by VLSI. Applications of VLSI are also discussed. The author argues that the growing innovative researches on VLSI array processors will play a central role in defining the algorithmic, architectural, and applicational trend of the future supercomputer technology.
The proceedings contain 30 papers. The topics discussed include: an analysis of computer architectural factors contributing to image processor capacity;a very large scale integration (VLSI) system for image reconstruc...
The proceedings contain 30 papers. The topics discussed include: an analysis of computer architectural factors contributing to image processor capacity;a very large scale integration (VLSI) system for image reconstruction from projections;parallel architecture for line-scanned images;multilevel architectures for imageprocessing.a prebuffer algorithm for instant display of volume data;a geometry processor for imageprocessing.and pattern recognition;prospects for adaptive window architectures;comparison between co-occurrence matrices, local histograms and curvilinear integration for texture characterization;refinement of spectral methods for use in texture analysis;and image segmentation by cluster analysis of high resolution textured SPOT images.
algorithms and programs of texture analysis and classification of two-dimensional fields in a digital complex of imageprocessing.are described. The principal objective of the algorithms is to investigate all aspects ...
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algorithms and programs of texture analysis and classification of two-dimensional fields in a digital complex of imageprocessing.are described. The principal objective of the algorithms is to investigate all aspects of the learning subsets of images and identify sets of features which effectively classify the data of remote photographs of the Earth's surface. The programs are capable of statistical analysis of the groups of objects that are formed, evaluation of the error probability of a Bayes classifier, and the choice of the most effective set of features in terms of class separability, with classification of objects by referring them to one of the classes formed.
The well-known advantages of pipelines systolic array architecture is applied for implementation of a second-order recursive digital filter. The proposed structure achieves five-fold increase in system throughput over...
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The well-known advantages of pipelines systolic array architecture is applied for implementation of a second-order recursive digital filter. The proposed structure achieves five-fold increase in system throughput over standard techniques, and two-fold increase over usual systolic approaches. In this letter, the data flow operation and the basic cell implementation for this design are presented.
We present the language SIGNAL which is a data flow-oriented real-time, synchronous, side effect-free language suited to the expression and recovery of the parallelism in signal or imageprocessing.algorithms. The lan...
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We present the language SIGNAL which is a data flow-oriented real-time, synchronous, side effect-free language suited to the expression and recovery of the parallelism in signal or imageprocessing.algorithms. The language is intended to be, at the same time, an executable simulation language, and a specification of a virtual machine implementing the algorithm. The language is semantically sound, and is suitable to perform program transforms-a major requirement when the ultimate goal is an aid to the architecture design.
A novel fine-grain parallel-processing.microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing.com...
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A novel fine-grain parallel-processing.microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing.computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing.tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing.is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and ‘ball-park’ performance figures are given.
image reconstruction by computer tomography provides a nonintrusive method of imaging the internal structure of objects. From measurements of radiation (e.g. X-rays or gamma rays) passed through an object, it is possi...
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image reconstruction by computer tomography provides a nonintrusive method of imaging the internal structure of objects. From measurements of radiation (e.g. X-rays or gamma rays) passed through an object, it is possible to reconstruct the internal structure. There is great interest in the potential of such methods in industrial applications but a number of problems need to be solved before these opportunities can be realised. The reconstruction process is computationally intensive and requires imaginative parallel processing.algorithms to attain ‘real-time’ performance. The work carried out has involved evaluating how these algorithms can be used in multiprocessor concurrent architectures to obtain rapid image reconstruction. A suitable computer architecture has been simulated in occam. This allows execution on a collection of transputers.
L’intérêt pour les systèmes de vision électroniques, au cours des 25 dernières années, a conduit à la réalisation de nombreux processeurs d’images. Leur étude pose en soi...
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L’intérêt pour les systèmes de vision électroniques, au cours des 25 dernières années, a conduit à la réalisation de nombreux processeurs d’images. Leur étude pose en soit un défi de taille qui complique inutilement l’accès au domaine. Cet article tente donc de résoudre le problème en présentant une analyse structurée des principales réalisations, afin d’obtenir une vision claire de la situation. Il appara?t alors que la plupart des processeurs ne découlent que de quelques architectures de base. Une analyse des tendances actuelles de développement est aussi présentée, ainsi que des suggestions pour la recherche future.
The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing.elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and ...
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The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing.elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing.elements. Packing 143K transistors on a 73 mm2silicon die, with 2.5 μm p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.
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