Typically, image and signal processing.require specialized computing systems that perform millions of floating point arithmetic operations rapidly and accurately. These systems must have large memories to store the ma...
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Typically, image and signal processing.require specialized computing systems that perform millions of floating point arithmetic operations rapidly and accurately. These systems must have large memories to store the massive amounts of data present in signals and images. And, software that takes advantage of a system's architecture is essential for maximum throughput. Multiprocessor systems can achieve high speed throughput for image and signal processing.by using multiple computational processors.
image reconstruction by computer tomography provides a nonintrusive method of imaging the internal structure of objects. From measurements of radiation (e.g. X-rays or gamma rays) passed through an object, it is possi...
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image reconstruction by computer tomography provides a nonintrusive method of imaging the internal structure of objects. From measurements of radiation (e.g. X-rays or gamma rays) passed through an object, it is possible to reconstruct the internal structure. There is great interest in the potential of such methods in industrial applications but a number of problems need to be solved before these opportunities can be realised. The reconstruction process is computationally intensive and requires imaginative parallel processing.algorithms to attain ‘real-time’performance. The work carried out has involved evaluating how these algorithms can be used in multiprocessor concurrent architectures to obtain rapid image reconstruction. A suitable computer architecture has been simulated in occam. This allows execution on a collection of transputers.
A computing architecture called DRAFT (Dynamically Reconfigurable architecture for Factoring Things) is presented which is used in parallel processing.of image data structures. It is shown that quadtree data structure...
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ISBN:
(纸本)0818607246
A computing architecture called DRAFT (Dynamically Reconfigurable architecture for Factoring Things) is presented which is used in parallel processing.of image data structures. It is shown that quadtree data structures can be processed efficiently on this parallel architecture. algorithms are given for constructing and pruning the quadtree structure and for finding neighbors in a parallel fashion. The computational requirements of the DRAFT system in imageprocessing.are examined and analyzed in detail.
The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing.elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and ...
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The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing.elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing.elements. Packing 143K transistors on a 73 mm2silicon die, with 2.5 μm p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.
Among all the numerous parallel structures that have been studied for and involved in imageprocessing. this article gives some elements for an answer to the problem of the choice of some architectures dedicated to Im...
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The authors present the PSI, a fast 16/32-bit VLSI microcomputer for digital signal processing. The PSI incorporates innovative architectural solutions to meet the high-throughput requirements of complex signal proces...
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The authors present the PSI, a fast 16/32-bit VLSI microcomputer for digital signal processing. The PSI incorporates innovative architectural solutions to meet the high-throughput requirements of complex signal processing.algorithms. The multimode internal architecture matches the inherent parallelism of the algorithms and the external architecture allows several processors and external peripheral and memory chips to be wired together. The resulting multiprocessor architecture behaves as a data-flow machine. A few examples of the kernel algorithms are presented and system architectures based on the PSI are described in some detail.
We describe the extension of the concepts of size distribution measurement from linear to non linear filtering and from binary to greyvalue imageprocessing. A size-height transform was developed in order to make a sp...
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Most algorithms for high,quality modeling and coding of stochastic sequences (speech or images) make extensive use of matrix operations. Because of the high computational complexity of these operations, the use of con...
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Most algorithms for high,quality modeling and coding of stochastic sequences (speech or images) make extensive use of matrix operations. Because of the high computational complexity of these operations, the use of conventional implementation techniques and architecture designs would almost certainly rule out such algorithms as candidates for real-time signal processing. In this paper, we present an algorithm and its mapping on a VLSI architecture for the solution of N (n +1) by (n +1) systems of linear equations, which arise from a speech coding algorithm. The systems of equations form an ordered set of equations and they mutually exhibit rank 1 differences. This property is exploited to obtain concurrently the solution of all equations. Via an analysis of the algebraic structure of the systems of equations, we succeed in reducing the complexity to a single matrix inversion, while enhancing the regularity of the algorithm, e.g., by including the back substitution in the main factorization loop. Next, we proceed to map the algorithm on VLS1 hardware, using a very systematic hierarchical temporal/structural decomposition/ partitioning approach. To achieve high throughput, we make extensive use of pipelining and show how a pipelined CORDIC processor element supports the desired operations. The complete equation solver is build around two pipelined CORDIC processor elements and two FIFO-type memories. The solver fits on three VLSI chips of size 6.5*6.5 mm 2 in a standard-slow-NMOS technology. The chips are of medium complexity and the resulting floorplan is shown. The resulting architecture achieves a very high throughput with minimal dataflow-oriented hardware.
For years, computer scientists and users have looked forward to the day when cheaper and more powerful computers would be brought to them by a new architecture called parallel processing. Parallel processing.puts hund...
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For years, computer scientists and users have looked forward to the day when cheaper and more powerful computers would be brought to them by a new architecture called parallel processing. Parallel processing.puts hundreds or thousands of smaller computers to work side by side, in parallel, in place of one larger, more expensive computer working a step at a time, serially. The basic idea behind parallel processing.is simple. A conventional serial machine takes all its data from a central store, which means that when working on many applications, such as imageprocessing. it spends most of its time retrieving data and little in calculating. Instead, a parallel processor breaks a problem into many pieces, and each subprocessor works on one piece of the problem with its own much smaller and handier memory. Furthermore, a parallel processor consisting of many small central processing.units should cost less than today's supercomputers.
A fine-grain-parallelism multiprocessor for digital signal processing.is currently under development. The architecture is the outgrowth of theoretical work on optimal multiprocessor realizations of digital signal proc...
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A fine-grain-parallelism multiprocessor for digital signal processing.is currently under development. The architecture is the outgrowth of theoretical work on optimal multiprocessor realizations of digital signal processing.algorithms. The architecture specifically supports systolic, data-driven, MIMD and cyclostatic processor realizations. The emphasis is on the latter, which are a class of solutions for which compilers have been designed to generate implementations that achieve several optimality criteria. An unconventionally large interprocessor communications bandwidth is provided in order to support the capability for practically achievement of optimal solutions.
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