The experimental Multi-microcomputing system SYSSIM, to be used in the Computer-Aided Control System Design (CACSD) and Interactive Real-Time Control System Simulation is presented in this paper. The digital controlle...
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The experimental Multi-microcomputing system SYSSIM, to be used in the Computer-Aided Control System Design (CACSD) and Interactive Real-Time Control System Simulation is presented in this paper. The digital controller is synthesized by using the (CACSD) programs developed for the SYSSIM system where they will later be simulated in real-time mode by synchronized parallel processing. SYSSIM aims at being an architecture system which can be reconfigured in such a way as to become the nucleus of a low-cost workstation for the development and test of control algorithms.
This paper develops an approach to deriving special FFT and convolution algorithms, considering the architecture of special-purpose DSP micros with a hardware multiplier and an adjacent accumulator. Because of the bui...
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This paper develops an approach to deriving special FFT and convolution algorithms, considering the architecture of special-purpose DSP micros with a hardware multiplier and an adjacent accumulator. Because of the build-in accumulator, it is possible to combine multiplications and additions into one operation, and hence the optimality criterion is redefined to minimize the total number of additions, multiplications and combined multiply-additions, which results in new interesting algorithms. The structure of the algorithms depends strongly on the nature of N - the sequence length. Where most conventional fast algorithms decompose convolutions completely, it turns out that because the adjacent accumulator can hides some of the additions, they should only be partly decomposed. The decomposition is done by index mapping and the implementation uses Winograd's ideas. Discrete Fourier transforms are also only partly decomposed, in contrast to most algorithms. The DFTs are converted into convolutions, and the convolutions are implemented as block processing. Comparisons show up to a 35 % improvement in execution speed.
Theoretical analysis of an ILAN model of MAGNET, an integrated network testbed, shows that the bandwidth freed up by video and voice calls during periods of little movement in the images and silence periods in the spe...
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ISBN:
(纸本)0892527420
Theoretical analysis of an ILAN model of MAGNET, an integrated network testbed, shows that the bandwidth freed up by video and voice calls during periods of little movement in the images and silence periods in the speech signals could be utilized efficiently for graphics and data transmission. Based on these investigations, an architecture supporting adaptive protocols that are dynamically controlled by the requirements of a fluctuating load and changing user environment has been advanced. To further analyze the behavior of the network, a real-time packetized video system has been implemented. This system is embedded in the real time multimedia workstation EDDY that integrates video, voice and data traffic flows. Protocols supporting variable bandwidth, constant quality packetized video transport are described.
Relaxation method attracts attention as an effective method in imageprocessing.and pattern recognition. From the first, the relaxation operation has been said to be capable of parallel processing. But previous hardwa...
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Relaxation method attracts attention as an effective method in imageprocessing.and pattern recognition. From the first, the relaxation operation has been said to be capable of parallel processing. But previous hardware implementations were specialized to each application. This paper presents a parallel architecture of a relaxation processor which can be applied to general use.
The paper presents a computer which employs massive parallelism. This massively parallel processing.computer (MPPC) manipulates arrays of 0s and 1s in contrast to conventional manipulation of bits. The proposed comput...
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The paper presents a computer which employs massive parallelism. This massively parallel processing.computer (MPPC) manipulates arrays of 0s and 1s in contrast to conventional manipulation of bits. The proposed computer will have a spatially parallel architecture that would enable it to recognize automatically in just milliseconds the details in satellite pictures. MPPC hardware is made up of 128 multiplied by 128 matrix of bit-serial processing.elements in an array unit (ARU) and its control - the array control unit (ACU). These are interfaced to a host controller computer (HCC). The instruction set can be divided into three basic classes viz. Boolean, simple near-neighbour, and recursive near neighbour.
This conference proceedings contains 14 papers, two of which are in abstract form only. The main subjects are local neighbourhood operators, display of digitalimage data, remote sensing, image thinning algorithms, re...
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ISBN:
(纸本)0869804731
This conference proceedings contains 14 papers, two of which are in abstract form only. The main subjects are local neighbourhood operators, display of digitalimage data, remote sensing, image thinning algorithms, realtime data compression, syntactic edge detection algorithms, parallel processing.image computers, computer vision systems, shape recognition, and characterisation of visual texture.
The problem of computing projection, of digitalimages is considered. algorithms are presented that are suitable for implementation in general-purpose imageprocessing.and image analysis pipeline architectures. Also, ...
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The problem of computing projection, of digitalimages is considered. algorithms are presented that are suitable for implementation in general-purpose imageprocessing.and image analysis pipeline architectures. Also, some new pipeline configurations are proposed that achieve a remarkable degree of parallelism in the computation of projection data and, in fact, of many other geometrical descriptors of digitalimages. In particular, random access memories and other dedicated hardware devices are not needed in these algorithms. The effectiveness of the approach and feasibility of the proposed architectures are demonstrated by running the algorithms in commercially available shortpipelines for imageprocessing.and analysis. Examples are shown of the use of projection data for machine vision applications.
This paper presents a new imageprocessing.system intends to enhance video images transmitted from remotely piloted vehicles (R. P. Vs), or any other airphotoes in real time. The objective was to select known algorith...
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ISBN:
(纸本)0892526149
This paper presents a new imageprocessing.system intends to enhance video images transmitted from remotely piloted vehicles (R. P. Vs), or any other airphotoes in real time. The objective was to select known algorithms of imageprocessing.techniques and to develop special purpose architecture, based on pipe line processor in hardware and top down structure design in software, in order to apply these algorithms in real time. The system operator is not required to have knowledge of imageprocessing. Interactive operations were chosen since successful image enhancement is based on the ability of the observer to detect information of interest in the final process image. The system architecture, the imageprocessing.moduls and the data base management are described briefly.
This conference proceedings contains 14 papers, two of which are in abstract form only. The main subjects are local neighborhood operators, display of digitalimage data, remote sensing, image thinning algorithms, rea...
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ISBN:
(纸本)0869804731
This conference proceedings contains 14 papers, two of which are in abstract form only. The main subjects are local neighborhood operators, display of digitalimage data, remote sensing, image thinning algorithms, realtime data compression, syntactic edge detection algorithms, parallel processing.image computers, computer vision systems, shape recognition, and characterization of visual texture.
The proceedings contain 22 papers. The topics discussed include: a dualistic model to describe computer architectures;modular real time architectures for image understanding applications;a high speed recirculating nei...
The proceedings contain 22 papers. The topics discussed include: a dualistic model to describe computer architectures;modular real time architectures for image understanding applications;a high speed recirculating neighborhood processing.architecture;system design for local neighborhood processing.the design of video processor in TV tracking system;a new architecture for real-time imageprocessing.advanced digital video processing.unit;obtaining feasible solutions in image restoration;a study of the discrete Hartley transform for image compression applications;block transform image compression by power spectrum fitting;and superfine laser position control using statistically enhanced resolution in real time.
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