Following the development of several high-speed imageprocessing.systems, it has been acknowledged that the only way to achieve real low power and system compactness is by using customized ICs. In an effort to reduce ...
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The filtering of digitalimages in both the spatial and frequency domain has become a prerequisite in many practical applications of digitalimageprocessing. In this presentation three pieces of commercially availabl...
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The filtering of digitalimages in both the spatial and frequency domain has become a prerequisite in many practical applications of digitalimageprocessing. In this presentation three pieces of commercially available 'firmware' - 'software controlled hardware' - will be discussed which provide fast yet flexible filtering capabilities. One of these units is specifically for frequency domain filtering, performing whole image fast fourier transforms and related algorithms in seconds. The other two illustrate quite different approaches to performing correlation and convolution in the spatial domain.
A class of features, called "edge features," has been developed and applied to several problems of practical interest in imageprocessing. These features are derived from a vector-valued function of the imag...
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A brief description is given of the scan line array processor (SLAP), a new architecture for image and vision processing. and its application to low-level vision computations is discussed. A SLAP is a SIMD machine wit...
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ISBN:
(纸本)0818606622
A brief description is given of the scan line array processor (SLAP), a new architecture for image and vision processing. and its application to low-level vision computations is discussed. A SLAP is a SIMD machine with one simple processor devoted to each pixel in a single image scan line. This structure has several features that make it very economical to build and use, and it supports efficient implementations of a wide variety of algorithms over a wide range of cost and performance. The good fit between the SLAP approach and VLSI technology promises to supply truly high-throughput imageprocessing.at unprecedented low cost. Although the authors concentrate on vision applications, SLAPs are also well suited for execution of many types of parallel algorithms and promise high throughput in graphics, signal processing. and coding applications.
The following topics are dealt with: speech recognition;digital filters;spectrum analysis;image coding;detection and estimation;geophysical imageprocessing.VLSI signal processors;speech coding;VLSI algorithms and sys...
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The following topics are dealt with: speech recognition;digital filters;spectrum analysis;image coding;detection and estimation;geophysical imageprocessing.VLSI signal processors;speech coding;VLSI algorithms and systolic arrays;parameter estimation;deconvolution;bandlimited extrapolation;speech analysis and reconstruction;time-frequency analysis and synthesis;array processing.and beam-forming;audio and electroacoustics;image estimation and restoration;speech enhancement and synthesis;transforms;spectral analysis;feature extraction, segmentation, and scene analysis;time-varying-signal modeling;reconstruction and tomography;vocal tract and speech analysis;adaptive filtering;multidimensional filtering;radar system identification;phonetic analysis and database;and quantization and nonlinear systems. 481 papers were presented, of which 472 are published in full in the present proceedings.
A performance study has been carried out for the ICL Distributed Array Processor (DAP) on some aspects of image analysis. The algorithms studied were the application of a Mexican-hat-shaped convolution, area filling, ...
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ISBN:
(纸本)0818606622
A performance study has been carried out for the ICL Distributed Array Processor (DAP) on some aspects of image analysis. The algorithms studied were the application of a Mexican-hat-shaped convolution, area filling, feature extraction, and classification via a statistical classifier. Some parts of the program have been implemented in Fortran on a VAX/780, and comparisons between the projected DAP assembler performance and the VAX performance indicate that a speedup of more than three orders of magnitude may be expected for the various stages of processing.
The Honeywell Parallel Programmable Processor (PPP) set of VHSIC chips is intended to provide a flexible architecture for two dimensional real-time imageprocessing. The chip set consists of three devices: the PPP, Se...
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ISBN:
(纸本)0892525991
The Honeywell Parallel Programmable Processor (PPP) set of VHSIC chips is intended to provide a flexible architecture for two dimensional real-time imageprocessing. The chip set consists of three devices: the PPP, Sequencer, and Arithmetic Generator. In performing an analysis of the use of these devices in an imageprocessing.application, the designer must often simulate the imaging algorithm so that it fits the architecture of the VHSIC devices. The authors describe a macro-model of the Honeywell PPP devices written in the DoD Ada language. The Ada model for the PPP uses the concurrency features of Ada to emulate the parallel processing.internal to the PPP devices. An imageprocessing.algorithm performed on two dimensional images using the Ada model is described. The Ada model is useful for understanding the processing.characteristics of algorithms when they are to be executed in the Honeywell PPP architecture.
A reconfigurable cellular array processor (RCAP) that is suitable for imageprocessing.is proposed. The system consists of memory-augmented processors that are connected by the omega networks. Two different structures...
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ISBN:
(纸本)0818606622
A reconfigurable cellular array processor (RCAP) that is suitable for imageprocessing.is proposed. The system consists of memory-augmented processors that are connected by the omega networks. Two different structures are implemented on the system: the mesh, and the 2**K -way tree. The algorithm for reconfiguring the system from the mesh structure to the quadtree structure is described. With this algorithm, the image can be processed from pixel-level to region-level successively. Thus, tremendous I/O overheads caused by data transfer between processors and the host computer can be avoided. A variety of imageprocessing.functions implemented on the system are mentioned.
The architecture is based upon a general, flexible core together with modular functional subunits. Configurations can address a wide range of applications and budgets. At one extreme we can configure a system to suppo...
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Diverse image understanding (IU) system applications and attendant reduced life cycle cost requirements call for real time system architectures which are increasingly flexible, maintainable, reprogrammable, and upgrad...
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