The following topics are dealt with: speech recognition;digital filters;spectrum analysis;image coding;detection and estimation;geophysical imageprocessing.VLSI signal processors;speech coding;VLSI algorithms and sys...
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The following topics are dealt with: speech recognition;digital filters;spectrum analysis;image coding;detection and estimation;geophysical imageprocessing.VLSI signal processors;speech coding;VLSI algorithms and systolic arrays;parameter estimation;deconvolution;bandlimited extrapolation;speech analysis and reconstruction;time-frequency analysis and synthesis;array processing.and beam-forming;audio and electroacoustics;image estimation and restoration;speech enhancement and synthesis;transforms;spectral analysis;feature extraction, segmentation, and scene analysis;time-varying-signal modeling;reconstruction and tomography;vocal tract and speech analysis;adaptive filtering;multidimensional filtering;radar system identification;phonetic analysis and database;and quantization and nonlinear systems. 481 papers were presented, of which 472 are published in full in the present proceedings.
A performance study has been carried out for the ICL Distributed Array Processor (DAP) on some aspects of image analysis. The algorithms studied were the application of a Mexican-hat-shaped convolution, area filling, ...
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ISBN:
(纸本)0818606622
A performance study has been carried out for the ICL Distributed Array Processor (DAP) on some aspects of image analysis. The algorithms studied were the application of a Mexican-hat-shaped convolution, area filling, feature extraction, and classification via a statistical classifier. Some parts of the program have been implemented in Fortran on a VAX/780, and comparisons between the projected DAP assembler performance and the VAX performance indicate that a speedup of more than three orders of magnitude may be expected for the various stages of processing.
The Honeywell Parallel Programmable Processor (PPP) set of VHSIC chips is intended to provide a flexible architecture for two dimensional real-time imageprocessing. The chip set consists of three devices: the PPP, Se...
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ISBN:
(纸本)0892525991
The Honeywell Parallel Programmable Processor (PPP) set of VHSIC chips is intended to provide a flexible architecture for two dimensional real-time imageprocessing. The chip set consists of three devices: the PPP, Sequencer, and Arithmetic Generator. In performing an analysis of the use of these devices in an imageprocessing.application, the designer must often simulate the imaging algorithm so that it fits the architecture of the VHSIC devices. The authors describe a macro-model of the Honeywell PPP devices written in the DoD Ada language. The Ada model for the PPP uses the concurrency features of Ada to emulate the parallel processing.internal to the PPP devices. An imageprocessing.algorithm performed on two dimensional images using the Ada model is described. The Ada model is useful for understanding the processing.characteristics of algorithms when they are to be executed in the Honeywell PPP architecture.
A reconfigurable cellular array processor (RCAP) that is suitable for imageprocessing.is proposed. The system consists of memory-augmented processors that are connected by the omega networks. Two different structures...
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ISBN:
(纸本)0818606622
A reconfigurable cellular array processor (RCAP) that is suitable for imageprocessing.is proposed. The system consists of memory-augmented processors that are connected by the omega networks. Two different structures are implemented on the system: the mesh, and the 2**K -way tree. The algorithm for reconfiguring the system from the mesh structure to the quadtree structure is described. With this algorithm, the image can be processed from pixel-level to region-level successively. Thus, tremendous I/O overheads caused by data transfer between processors and the host computer can be avoided. A variety of imageprocessing.functions implemented on the system are mentioned.
The architecture is based upon a general, flexible core together with modular functional subunits. Configurations can address a wide range of applications and budgets. At one extreme we can configure a system to suppo...
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Diverse image understanding (IU) system applications and attendant reduced life cycle cost requirements call for real time system architectures which are increasingly flexible, maintainable, reprogrammable, and upgrad...
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The mathematical morphological operations on grey scale images require the selections of the minimum or the maximum value within the windows set by structuring elements. This paper deals with the structuring elements ...
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ISBN:
(纸本)0892526106
The mathematical morphological operations on grey scale images require the selections of the minimum or the maximum value within the windows set by structuring elements. This paper deals with the structuring elements which are three dimensional with flat top and infinite height. The flat top region can be various shapes of one or two dimensions such as line segment, hexagon, octagon or circle. This paper describes the optimal implementation of the morphological operations with such structuring elements, an iterative method which combines controlled image shiftings and comparisons between the original and shifted images. It is an effective imageprocessing.method without a cytocomputer architecture.
Many problems in low- and medium-level vision have low communication requirements. These problems, when solved on a two-dimensional mesh connected computer, require OMEGA (N**1 **/ **2 ) time owing to the time require...
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ISBN:
(纸本)0818606622
Many problems in low- and medium-level vision have low communication requirements. These problems, when solved on a two-dimensional mesh connected computer, require OMEGA (N**1 **/ **2 ) time owing to the time required for information flow over long distance. Such problems can be solved faster by using additional shared buses and/or additional links to facilitate fast long-distance communication. The authors present some enhanced mesh organizations with efficient parallel algorithms for determining geometric properties of images. The results are compared with other parallel models, such as pyramid computers, used for imageprocessing.
The authors propose an efficient VLSI multiprocessor architecture which consists of n processors and n**2 memory modules interconnected by a simplified mesh network. This reduced mesh architecture is especially suitab...
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ISBN:
(纸本)0818606428
The authors propose an efficient VLSI multiprocessor architecture which consists of n processors and n**2 memory modules interconnected by a simplified mesh network. This reduced mesh architecture is especially suitable for VLSI implementation due to its reduced number of processors and communication links. The system is specially designed for high-level signal/imageprocessing.applications, where extensive numerical computations are needed. Many computations, such as those often encountered in 2-D image transformations, FFT, and least-square data fitting, can be solved efficiently and elegantly on the proposed system. The system architecture is flexible and matches with a variety of important numerical algorithms. The proposed multiprocessor has the potential of achieving a linear speedup factor of n over a uniprocessor system.
A simplified shared-memory multiprocessor organization is proposed for VLSI implementation. This architecture can realize many scientific computations with an O(n) speedup, where n is the number of processors in the s...
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ISBN:
(纸本)0818606371
A simplified shared-memory multiprocessor organization is proposed for VLSI implementation. This architecture can realize many scientific computations with an O(n) speedup, where n is the number of processors in the system. Many problems including matrix computations, fast Fourier transform, sorting, and partial differential equations can be solved efficiently and elegantly on the proposed system. Systematic methods are developed for mapping parallel algorithms designed for the mesh and the hypercube multiprocessor architectures into the proposed architecture. The proposed system has significantly reduced hardware demand and thus is suitable for VLSI implementation using a limited chip set.
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