This paper describes a bus-oriented hardware architecture for the acquisition, processing.and display of high-resolution two dimensional image data patterns. The system contains dedicated bipolar processors for image ...
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The article describes a system able to process gray-level image data of a high spatial resolution at a high speed. A large number of data reduction algorithms are implemented by means of a table driven architecture. T...
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Despite the large degrees of parallelism present in the structure of the data and operations, it is not clear what parallel architecture is best suited for a given imageprocessing.application. This paper proposes a m...
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A general purpose, high-speed imageprocessing.system with a time shared multiframe data bus architecture and with multi-processors-MFIP-has been developed. Massive image data can be transferred from/to multiple memor...
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Many applications in visual inspection and in robotvision require a very fast interpretation and evaluation of images, so that industrial processes should not be slowed down. In this paper an image computer architectu...
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作者：
Price, Eugene V.Gould
Inc. DeAnza Imaging and Graphics Division 1870 Lundy Avenue San JoseCA95131 United States
A two-dimensional FFT algorithm has been implemented on a pipelined image processor with parallel feedback image data paths. The transform of a 512x512 pixel image, or say 256 images 32x32 pixels in size, can be carri...
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A hardware architecture for real-time image resampling has been developed which will support a wide range of image resampling tasks arising in remote sensing applications-In particular, local spatial sampling errors c...
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This paper deals with the development of a general architecture for imageprocessing.after considering important aspects of imageprocessing.algorithms commonly used today. The algorithms are linked by mutual operatio...
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ISBN:
(纸本)0892525398
This paper deals with the development of a general architecture for imageprocessing.after considering important aspects of imageprocessing.algorithms commonly used today. The algorithms are linked by mutual operations and using this fact leads to architecture suitable for a wide variety of operations. An architecture will be developed that spans a wide range of functionality through systematic expansion, making it fit for low cost production and commercial consumption. It is also the intent of this paper to introduce a general theory about such systems, and to provoke further thinking along these lines.
It is shown that the mesh-connected computer can be used for more than low-level, local imageprocessing. The authors present optimal algorithms, in the O-notational sense, for determining several fundamental geometri...
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ISBN:
(纸本)081860560X
It is shown that the mesh-connected computer can be used for more than low-level, local imageprocessing. The authors present optimal algorithms, in the O-notational sense, for determining several fundamental geometric properties. For example, given a figure represented by the Cartesian coordinates of O(n) planar points, distributed one point per processor on a mesh-connected computer, theta (n**1 **/ **2 ) algorithms are given for identifying the convex hull of the figure and for determining a smallest enclosing box of the figure. Given two such figures, theta (n**1 **/ **2 ) algorithms are given to decide if the two figures are linearly separable. Also given is a theta (n**1 **/ **2 ) algorithm for determining the nearest neighbor of each of the O(n) planar points. Since any serial computer has a best-case time of theta (n) when processing.O(n) points, these algorithms show that the mesh-connected computer provides significantly better solutions to these problems.
作者：
Kung, H.T.Carnegie-Mellon Univ
Dep of Computer Science Pittsburgh PA USA Carnegie-Mellon Univ Dep of Computer Science Pittsburgh PA USA
A 32-bit floating-point systolic array processor is currently being built at CMU, using off-the-shelf integrated circuits. The 10-cell processor, with about 120 packages in each cell, can process 1024-point complex FF...
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ISBN:
(纸本)0818605456
A 32-bit floating-point systolic array processor is currently being built at CMU, using off-the-shelf integrated circuits. The 10-cell processor, with about 120 packages in each cell, can process 1024-point complex FFTs at a rate of one FFT every 600 mu s. Under program control, the same processor can perform many other primitive computations in signal and imageprocessing. including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. This particular systolic array processor is called the Warp processor, because it can perform various transformations at a very high speed. The Warp processor has an extremely simple architecture. The processor is a linear array of processing.elements that takes inputs from one end and produces outputs at the other end, with data and control all flowing in one direction. A key reason that this simple processor is expected to be useful is the availability of a large set of systolic algorithms or systolic array designs suitable for the processor. This paper describes several such systolic algorithms in the area of signal and imageprocessing.
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