Many applications in visual inspection and in robotvision require a very fast interpretation and evaluation of images, so that industrial processes should not be slowed down. In this paper an image computer architectu...
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作者：
Price, Eugene V.Gould
Inc. DeAnza Imaging and Graphics Division 1870 Lundy Avenue San JoseCA95131 United States
A two-dimensional FFT algorithm has been implemented on a pipelined image processor with parallel feedback image data paths. The transform of a 512x512 pixel image, or say 256 images 32x32 pixels in size, can be carri...
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A hardware architecture for real-time image resampling has been developed which will support a wide range of image resampling tasks arising in remote sensing applications-In particular, local spatial sampling errors c...
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This paper deals with the development of a general architecture for imageprocessing.after considering important aspects of imageprocessing.algorithms commonly used today. The algorithms are linked by mutual operatio...
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ISBN:
(纸本)0892525398
This paper deals with the development of a general architecture for imageprocessing.after considering important aspects of imageprocessing.algorithms commonly used today. The algorithms are linked by mutual operations and using this fact leads to architecture suitable for a wide variety of operations. An architecture will be developed that spans a wide range of functionality through systematic expansion, making it fit for low cost production and commercial consumption. It is also the intent of this paper to introduce a general theory about such systems, and to provoke further thinking along these lines.
It is shown that the mesh-connected computer can be used for more than low-level, local imageprocessing. The authors present optimal algorithms, in the O-notational sense, for determining several fundamental geometri...
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ISBN:
(纸本)081860560X
It is shown that the mesh-connected computer can be used for more than low-level, local imageprocessing. The authors present optimal algorithms, in the O-notational sense, for determining several fundamental geometric properties. For example, given a figure represented by the Cartesian coordinates of O(n) planar points, distributed one point per processor on a mesh-connected computer, theta (n**1 **/ **2 ) algorithms are given for identifying the convex hull of the figure and for determining a smallest enclosing box of the figure. Given two such figures, theta (n**1 **/ **2 ) algorithms are given to decide if the two figures are linearly separable. Also given is a theta (n**1 **/ **2 ) algorithm for determining the nearest neighbor of each of the O(n) planar points. Since any serial computer has a best-case time of theta (n) when processing.O(n) points, these algorithms show that the mesh-connected computer provides significantly better solutions to these problems.
作者：
Kung, H.T.Carnegie-Mellon Univ
Dep of Computer Science Pittsburgh PA USA Carnegie-Mellon Univ Dep of Computer Science Pittsburgh PA USA
A 32-bit floating-point systolic array processor is currently being built at CMU, using off-the-shelf integrated circuits. The 10-cell processor, with about 120 packages in each cell, can process 1024-point complex FF...
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ISBN:
(纸本)0818605456
A 32-bit floating-point systolic array processor is currently being built at CMU, using off-the-shelf integrated circuits. The 10-cell processor, with about 120 packages in each cell, can process 1024-point complex FFTs at a rate of one FFT every 600 mu s. Under program control, the same processor can perform many other primitive computations in signal and imageprocessing. including two-dimensional convolution and complex matrix multiplication, at a rate of 100 MFLOPS. This particular systolic array processor is called the Warp processor, because it can perform various transformations at a very high speed. The Warp processor has an extremely simple architecture. The processor is a linear array of processing.elements that takes inputs from one end and produces outputs at the other end, with data and control all flowing in one direction. A key reason that this simple processor is expected to be useful is the availability of a large set of systolic algorithms or systolic array designs suitable for the processor. This paper describes several such systolic algorithms in the area of signal and imageprocessing.
The MATRA developped CLADYN compressor has been presented. It features the best possible use of the topological properties of a color picture. The compression is performed independently on spatial blocks of 4 lines of...
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ISBN:
(纸本)0818605456
The MATRA developped CLADYN compressor has been presented. It features the best possible use of the topological properties of a color picture. The compression is performed independently on spatial blocks of 4 lines of data. The quantization is truly adaptive to the block statistics. A high compression ratio is obtained. The compression strategy does permit a modular hardware architecture and relatively slow parallel processing. The compressor is basically robust to the propagation of transmission errors and output fixed length words.
Several pyramid computer algorithms are presented for deciding convexity, identifying extreme points of a convex hull, and using extreme points. For a pyramid computer with a base of n processing.elements arranged in ...
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ISBN:
(纸本)081860560X
Several pyramid computer algorithms are presented for deciding convexity, identifying extreme points of a convex hull, and using extreme points. For a pyramid computer with a base of n processing.elements arranged in a square, the algorithms' times range from theta (log(n)) time to find the extreme points of a convex figure in the digitized picture, to theta (n**1 **/ **6 ) time to find the diameter of a figure, to theta (n**1 **/ **2 ) time to find, for each label, the extreme points of the processing.elements with that label. The results show the sensitivity of efficient pyramid algorithms to the rate at which the essential data can be reduced, and also show that a wide variety of techniques are needed to make full and efficient use of the pyramid architecture.
作者：
McFarland, W.D.Myers, J.W.Univ of Missouri
Electrical & Computer Engineering Dep Columbia MO USA Univ of Missouri Electrical & Computer Engineering Dep Columbia MO USA
The authors report on the development of a programmable parallel image processor that utilizes a five image-line pipeline buffer and nine sets of bit-slice microprocessors (16-bits wide), configured to operate on nine...
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ISBN:
(纸本)081860560X
The authors report on the development of a programmable parallel image processor that utilizes a five image-line pipeline buffer and nine sets of bit-slice microprocessors (16-bits wide), configured to operate on nine programmable neighborhoods in parallel. The application algorithms are microprogrammable from a host computer and may consist of operations, logical and arithmetic, defined over a number of possible neighborhoods. The design affords generality with real-time or near-real-time processing.for digitalimages up to 512 multiplied by 512 multiplied by 8 bits.
The following topics are dealt with: scientific computation;distributed systems;interconnection;artificial intelligences;numeric computation;performance modeling;fault tolerance;imageprocessing.applications;queuing a...
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ISBN:
(纸本)081860560X
The following topics are dealt with: scientific computation;distributed systems;interconnection;artificial intelligences;numeric computation;performance modeling;fault tolerance;imageprocessing.applications;queuing analysis;databases;vector machines;theory;scheduling;computer networks;array computations;languages;matrix computations;algorithms;simulation;memory systems;and data flow. 89 papers were presented, of which all are published in full in the present proceedings.
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