The design is discussed of a large scale Content Addressable Array Parallel Processor (CAAPP) for low, medium and high level vision processing. This new architecture combines associative processing.with global broadca...
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ISBN:
(纸本)0892525398
The design is discussed of a large scale Content Addressable Array Parallel Processor (CAAPP) for low, medium and high level vision processing. This new architecture combines associative processing.with global broadcast and response to and from an array of cells, and array processing.via local cellular square neighborhood computation. The capabilities of the CAAPP allow one to close the feedback loop between high level processing.and low level processing.by supporting communication between different representations of an image. The CAAPP would provide a means of mapping the signal level (iconic) pixel-based representation of an image into a symbolic intermediate level representation suitable for high level vision processing.
An evaluation was performed to characterize a new digital imaging system, the System One, DigiRad, Inc. and its imageprocessing.capabilities. This evaluation included reproducibility, dynamic range, linearity and the...
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ISBN:
(纸本)0892525398
An evaluation was performed to characterize a new digital imaging system, the System One, DigiRad, Inc. and its imageprocessing.capabilities. This evaluation included reproducibility, dynamic range, linearity and the effects on several image recording systems. Results show that the System One dynamic range is limited to 1300 levels in the range of 0. 0 to 2. 8 optical density units. It was observed that within this range, the System One response was approximately linear and reproducible within plus or minus 1%. The system spatial resolution limit is between 3. 0 and 3. 5 1p/mm. All processing.algorithms applied to digitized images of bar pattern film images degraded the resolution as compared to the images with no post processing. Improvements in System One are expected and will be evaluated as soon as they are available.
Denser and faster bipolar integrated circuits have promoted the construction of truly useful building blocks for digital-signal processing. Whole signal-processing.subsystems can now be built on a single chip, and sev...
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Denser and faster bipolar integrated circuits have promoted the construction of truly useful building blocks for digital-signal processing. Whole signal-processing.subsystems can now be built on a single chip, and several linked subsystems can provide parallel processing.at high data rates. Gate-array circuits, especially, give those who design such systems a flexible way of exploiting high-speed bipolar technology. The architecture of a Fast Fourier Transform (FFT) chip is described as only one example of the many gate-array applications for signal processing.digital filters, image processors, and graphics-display systems can all be implemented with gate arrays, and all can therefore achieve fast processing.rates, low power dissipation, and physical compactness.
作者：
Gupta, AnoopCarnegie-Mellon Univ
Dep of Computer Science Pittsburgh PA USA Carnegie-Mellon Univ Dep of Computer Science Pittsburgh PA USA
DADO is a highly parallel tree-structured architecture designed to execute production systems. The author analyzes the performance of DADO when executing OPS5 production system programs. The analysis is based on the p...
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ISBN:
(纸本)081860560X
DADO is a highly parallel tree-structured architecture designed to execute production systems. The author analyzes the performance of DADO when executing OPS5 production system programs. The analysis is based on the predicted performance of three different algorithms for implementing production systems on DADO. The analysis shows that the large-scale parallelism in DADO is not very effective for executing OPS5-like production systems. The reasons are: (1) actions of production in OPS5 programs do not have global effects, but only affect a small number of other productions;and (2) large-scale parallelism almost always implies that the individual processing.elements are weak. Since only a small number of productions are affected every cycle, only a few of the large number of processing.elements perform useful work. Furthermore, since the individual processing.elements are weak, the performance is worse than if a small number of powerful processors are used. The tree-structured topology of the DADO architecture is not found to be a bottleneck.
Template-controlled or data driven architecture is described as that which achieves concurrent operation by using a pipeline technique through data flow operation graph representation. The processing.capability, flexi...
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Template-controlled or data driven architecture is described as that which achieves concurrent operation by using a pipeline technique through data flow operation graph representation. The processing.capability, flexibility and suitability of this processor, which has been developed for imageprocessing. are evaluated through fundamental imageprocessing. such as sharpening or smoothing operations, two-dimensional Fast Fourier Transform, Affine Transformation, etc. The bus transfer capability for ring bus architecture used is analyzed approximately by a simple stochastic process model. It is confirmed through several imageprocessing.experiments that TIP-1 is suitable for computing the iterative operation and can be flexibly applied to new algorithms in large processing.
A method for the systematic study of parallel signal processor architectures and signal processing.algorithms is presented. The method is independent of presently available technology. The method is based on project m...
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A method for the systematic study of parallel signal processor architectures and signal processing.algorithms is presented. The method is independent of presently available technology. The method is based on project management techniques and has been adapted to meet the requirements of signal processing. It permits the comparison of different signal processing.algorithms with regard to minimal calculation time, using the parallelism inherent to the algorithm itself, and the optimal implementation of the algorithm on a given signal processor architecture.
Real time machine vision in mobile robots requires pre-processing.of images at speeds well in excess of one billion operations per second, depending on the resolution of the image plane. To obtain such high speed in a...
Real time machine vision in mobile robots requires pre-processing.of images at speeds well in excess of one billion operations per second, depending on the resolution of the image plane. To obtain such high speed in a compact, light-weight, and low-power computing system, alternatives to the standard serial digital processor are currently being explored. The spatially parallel architecture, in which the inter-processor communication structure reflects the topology of the focal plane mosaic of elemental sensors, is organized in a way natural for image pre-processing. The most logical place for the processor array is the imaging focal plane. Such positioning avoids the serial encoding and transmission of the inherently parallel input data, but the available real-estate places a premium on processor simplicity and innovation. In this dissertation, an analog processor based on the manipulation of discrete charge packets in a semiconductor is advocated. Such a processor shows promise for high density focal plane computing. The work focuses on the basic building blocks of the charge-coupled computer, a charge packet differencer/replicator and a charge packet magnitude comparator. The former is implemented in a novel circuit in an inherently linear and compact way through the use of three-dimensional charge coupling. Also investigated in the course of this research was the bistable metal/tunnel-oxide/semiconductor (MTOS) junction. The application of this device as a charge packet magnitude comparator was explored by utilizing its hot electron impact ionization internal positive feedback mechanism. The control circuitry integrated with the MTOS junction provided a unique opportunity to investigate the internal charging and discharging currents of the thin oxide capacitor. Using a novel charge packet injection technique, the dynamic response of the junction was studied and a measure of the oxide hole transport current and hot tunneling electron induced impact ionization curr
A study was made by the author on stability conditions for the two-dimensional digital filters that are required for imageprocessing.algorithms for testing the stability of such filters as mentioned above, can be ob...
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A study was made by the author on stability conditions for the two-dimensional digital filters that are required for imageprocessing.algorithms for testing the stability of such filters as mentioned above, can be obtained by applying T. S. Huang's theorem. This theorem, however, has not been proved completely by Huang, and various proofs by use of the maximum principle have been proposed. A new proof applying the principle of analytic continuation is presented.
Signal- and image-processing.system design is simplified by using a 5-port, 8-register IC which permits design digital filters than can be reconfigured by reprogramming rather than by rewiring. Because the IC allows s...
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Signal- and image-processing.system design is simplified by using a 5-port, 8-register IC which permits design digital filters than can be reconfigured by reprogramming rather than by rewiring. Because the IC allows simultaneous use of its five ports, it eliminates interference between I/O or memory transfers and arithmetic operations. The simultaneous use of ports is the key feature. For example, while two read ports source operands to an arithmetic-logic unit (ALU) or multiplier, and a third write port records the result, the remaining two ports allow unimpeded data movement to external memory. These external data accesses do not interfere with arithmetic operations, so no Wait states or No Op cycles commonly found in less flexible architectures are needed. This leads to the increase of throughput by as much as a factor of two for some algorithms. In addition, the device's eight 8-bit registers can be expanded for greater word width or memory depth.
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