A two-dimensional FFT algorithm has been implemented on a pipelined image processor with parallel feedback image data paths. The transform of a 512 multiplied by 512 pixel image, or say 256 images 32 multiplied by 32 ...
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ISBN:
(纸本)0892524707
A two-dimensional FFT algorithm has been implemented on a pipelined image processor with parallel feedback image data paths. The transform of a 512 multiplied by 512 pixel image, or say 256 images 32 multiplied by 32 pixels in size, can be carried out in one minute (excluding the transpose of the image). The image-processor architecture lends itself very well to some portions of the FFT computation;other portions suggest directions for future hardware development.
A novel architecture has been proposed based on the C-MOVE microprocessor for the fast and efficient parallel structural decomposition, W-H transform and encoding of digitalimages. A hierarchical and reconfigurable t...
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A novel architecture has been proposed based on the C-MOVE microprocessor for the fast and efficient parallel structural decomposition, W-H transform and encoding of digitalimages. A hierarchical and reconfigurable tree of interconnected processors is used to implement the W-H transform of an image which is already preprocessed and decomposed into a succession of consecutive “quadrant” sub-pictures. The regular decomposition procedure is followed to develop the quad-tree structure associated with a given image. Then a parallel algorithm is developed for the realization of the W-H transform of the given image. The W-H transform of the whole picture can be implemented by parallel processing. The C-MOVE architecture has been invoked for the realization of the above mentioned scheme. The C-MOVE architecture can prove to be extremely economical and fast, especially when a large number of parallel processors is utilized. The tree-structure of the decomposed picture and the proposed hierarchically distributed processing.scheme match very well, resulting in a very flexible and adaptable architecture for implementing an imageprocessing.scheme. The proposed scheme uses C-MOVE processors to implement all the modules of the system. The architecture presented exhibits a high degree of parallelism with the main processing.modules sharing the same main memory and exchanging data over the common very high speed bus, under the control of the master-controller processor. Each module works independently on the assigned task once the data and instruction string have been loaded in its part of memory. Meanwhile, the picture preprocessing.module is freed to proceed on the next step of the regular decomposition algorithm.
This paper acknowledges that digitalimageprocessing.systems no longer are limited to pure research or prototype status, but rather are cost-effective, accurate and efficient enough to have become a category of quasi...
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ISBN:
(纸本)0892524707
This paper acknowledges that digitalimageprocessing.systems no longer are limited to pure research or prototype status, but rather are cost-effective, accurate and efficient enough to have become a category of quasi-standard instrumentation in the fields of diagnostic medical imaging, visual inspection, remote sensing, geophysics, data encoding and decoding, and other fields. A new architectural concept incorporates the most recent advances in microprocessor technology: high-speed, specialized processors, often with local intelligence;large-scale direct-mapped memory;and multiple-bus and multitasking capabilities within a stand-alone device. This architecture is described as an alternative to the traditional configurations in which digitalimage generators, CPU, memory, special processors and peripherals exist as cable-length devices.
In this paper an image computer architecture is proposed, which is optimalized for two classes of typical imageprocessing.tasks, required in visual inspection and robotvision. Time-filtering, motion analysis, stereo-...
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ISBN:
(纸本)0892524707
In this paper an image computer architecture is proposed, which is optimalized for two classes of typical imageprocessing.tasks, required in visual inspection and robotvision. Time-filtering, motion analysis, stereo-vision, image compression, matching are examples of a first class of imageprocessing.tasks. To a second class of imageprocessing.tasks belongs feature extraction;in contrast with the preceding, this processing.requires only one image. The basic element of the system is a fast image Bus (IBUS) which is a reflection of the needs of parallel access and random access processing.: four differently programmable data channels, two address busses and data-to-address feedback capabilities. The system itself is modular to allow minimum configurations in a wide variety of industrial visual inspection tasks.
In this paper several algorithms for skeletonizing a three-dimensional (3-D) pictorial data are proposed with experimental results to provide ideas on what kinds of operations are required and what the computation tim...
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ISBN:
(纸本)0892524707
In this paper several algorithms for skeletonizing a three-dimensional (3-D) pictorial data are proposed with experimental results to provide ideas on what kinds of operations are required and what the computation time amounts to for processing.3-D images. algorithms discussed here include shrinking, thinning, distance transformation and border following.
Despite the numerous advantages of digital signal processing.(DSP), and the existence of a wealth of sophisticated algorithms, the widespread application of DSP has been hindered by a shortage of cost-effective digita...
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Despite the numerous advantages of digital signal processing.(DSP), and the existence of a wealth of sophisticated algorithms, the widespread application of DSP has been hindered by a shortage of cost-effective digital hardware for volume use. Now, with the availability of low-cost high-speed VLSI circuits, such as the Texas Instruments TMS320, the virtues and power of DSP are ready for realtime signal processing.applications. Development of the single-chip TMS320 DSP computer began in the late 1970s. The architecture, key novel features, instruction set and capabilities of this device are examined. Support software and hardware development tools for the TMS320 are also included with some of its applications. Typical areas of application of the TMS320 include speech signal processing. telecommunications, robotics, radar signal and sonar signal processing. seismology, imageprocessing. audio recording and reproduction, biomedical instrumentation, acoustic noise measurements and automatic test equipment.
Speckles appearing in synthetic aperture radar (SAR) images are generated by the coherent processing.of radar signals. Basically the speckles have the nature of a multiplicative noise. A simple and effective method of...
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Speckles appearing in synthetic aperture radar (SAR) images are generated by the coherent processing.of radar signals. Basically the speckles have the nature of a multiplicative noise. A simple and effective method of smoothing speckle-corrupted images by a digital computer is discussed, based on the recently developed sigma filter. The sigma filter is motivated by the sigma probability of a Gaussian distribution. The pixel to be processed is replaced by an advantage of those neighboring pixels having their gray level within two noise standard deviations from that of the concerned pixel. Consequently the speckles are suppressed without blurring edges and fine detail. Several Seasat SAR images are used for illustration, and comparisons are made with several noise-smoothing algorithms. Extensions of this algorithm to contrast enhancement and signal-dependent noise filtering are also presented. This algorithm is computationally efficient, and has the potential to achieve real or near real-time processing.
This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of imageprocessing.operations where high per...
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This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of imageprocessing.operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.
Popular approaches to speeding up scan conversion often employ parallel processing. Recently, several special-purpose parallel architectures have been suggested. The authors propose an alternative to these systems: th...
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Popular approaches to speeding up scan conversion often employ parallel processing. Recently, several special-purpose parallel architectures have been suggested. The authors propose an alternative to these systems: the general-purpose ultracomputer, a parallel processor with many autonomous processing.elements and a shared memory. The 'serial semantics/parallel execution' feature of this architecture is exploited in the formulation of a scan conversion algorithm. Hidden surfaces are removed using a single scanline, z-bufffer algorithm. Since exact anti-aliasing is inherently slow, a novel parallel anti-aliasing algorithms is presented in which subpixel coverage by edges is approximated using a look-up table. The algorithm is fast and accurate, it is attractive even in a serial environment, and it avoids several artifacts that commonly occur in animated sequences.
In imageprocessing. one of the most simple representation form of images is a binary or trinary vector representation. The authors introduce a new transform of trinary vectors called pseudo-Hadamard transform. This t...
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ISBN:
(纸本)0892524707
In imageprocessing. one of the most simple representation form of images is a binary or trinary vector representation. The authors introduce a new transform of trinary vectors called pseudo-Hadamard transform. This transform is a map of a trinary vector space into itself and has similar properties of the Hadamard transform. The authors show a factorization method of the Hadamard transform, callled the Good's formula and define the pseduo-Hadamard transform using this formula.
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