An interactive imageprocessing.system was set up to provide easy use of standard methods and their rapid execution. Point operations and linear and non-linear neighborhood operations were implemented on the display s...
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ISBN:
(纸本)0892524707
An interactive imageprocessing.system was set up to provide easy use of standard methods and their rapid execution. Point operations and linear and non-linear neighborhood operations were implemented on the display system for interger valued images and on the host for their floating point representation. Fourier domain processing.was accelerated by using the refresh memories for auxiliary direct access storage and by computing the FFT with assembly coded routines. Topological operations for segmentation of binary images are done in the display system. image classification with instant display of the results equally relies on the display hardware.
Mathematical Morphology is an algebraic language of imageprocessing.based on set-theoretic constructs. The operations of mathematical morphology are easily implemented in cellular logic image processors like the CLIP...
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ISBN:
(纸本)0892524707
Mathematical Morphology is an algebraic language of imageprocessing.based on set-theoretic constructs. The operations of mathematical morphology are easily implemented in cellular logic image processors like the CLIP or Cytocomputer. Drawbacks of arrays and pipelines serve as impetus for the design of several other cellular logic image processor architectures.
An integrated document editing and organizing system (IDEOS) has been developed. This system offers various functions required for document processing. It can manipulate various data forms (text, image and graphics) a...
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ISBN:
(纸本)0892524707
An integrated document editing and organizing system (IDEOS) has been developed. This system offers various functions required for document processing. It can manipulate various data forms (text, image and graphics) appearing in a document. It has real time imageprocessing.functions for the flexible formatting. In this system, the document is handled by hierarchic structure and is described by a hierarchical descriptor, which corresponds to the document structure. The effectiveness of this system has been evaluated utilizing two different kinds of applications.
A pipelined image processor has been developed to improve and analyse grey level images from electron microscopes. It uses high speed video processing.techniques in an image flow system, where image data can be circul...
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ISBN:
(纸本)0892524707
A pipelined image processor has been developed to improve and analyse grey level images from electron microscopes. It uses high speed video processing.techniques in an image flow system, where image data can be circulated at variable rates (dc to 10MHz) through a series of firmware processors in a recursive fashion around a digital framestore. The commercial system is proving invaluable in the quality assurance of photoresist material where such processing.is revealing features not before visible with traditional techniques. This approach is of general value where standard EM methods have an adverse effect on the specimen under investigation, resulting in poor signal quality.
A cellular logic operation traditionally consists of the parallel application of a local image transformation at all cells of a two dimensional array. In order to compute certain global image properties efficiently, i...
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ISBN:
(纸本)0892524707
A cellular logic operation traditionally consists of the parallel application of a local image transformation at all cells of a two dimensional array. In order to compute certain global image properties efficiently, it sometimes behooves one to extend the notion of an operation so that it operates on a hierarchical domain rather than just an image. In this paper, the definitions for hierarchial cellular logic operations are given and applied to the problem of selecting key pixels of a binary image. Such key pixels may be used as features themselves orused as seed points for object extraction algorithms.
A general purpose, high-speed imageprocessing.system with a time shared multiframe data bus architecture and with multi-processors - MFIP - has been developed. Massive image data can be transferred from/to multiple m...
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ISBN:
(纸本)0892524707
A general purpose, high-speed imageprocessing.system with a time shared multiframe data bus architecture and with multi-processors - MFIP - has been developed. Massive image data can be transferred from/to multiple memory modules to/from multi-processors through the high-speed time shared multi-frame data bus (40 MW/sec). The system is built up, centering on 2MW large image memory consisting of eight memory modules with 256KW (1W equals 16 bits). image memory can be expanded up to 8MW, i. e. , 32 memory modules. This paper describes the gross architecture of MFIP, and functional and operational features of the high-speed time shared multiframe data bus. Then design concept and manufacture of two imageprocessing.units, A and B in the system are presented.
An image Pipeline Processor (IPP) has been designed utilizing data flow architecture and pipelined structure. The IPP, modularized into several functional blocks which operate concurrently, has realized high level par...
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ISBN:
(纸本)0444867511
An image Pipeline Processor (IPP) has been designed utilizing data flow architecture and pipelined structure. The IPP, modularized into several functional blocks which operate concurrently, has realized high level parallel processing. Moreover, by connecting multiple IPP's in cascade, a multiprocessor system can be easily constructed to achieve the required performance. The IPP is suitable for iterative operations on a large amount number of data, such as imageprocessing. In this paper, the architecture, design methodology, functional assembler language and performance of the IPP are described.
A hardware architecture for real-time image resampling has been developed which will support a wide range of image resampling tasks arising in remote sensing applications. In particular, local spatial sampling errors ...
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ISBN:
(纸本)0892524707
A hardware architecture for real-time image resampling has been developed which will support a wide range of image resampling tasks arising in remote sensing applications. In particular, local spatial sampling errors caused by misalignment of sensor arrays and optical defects, plus global spatial sampling errors caused by platform pointing errors, can be simultaneously rectified. This is achieved by referring all sample errors to the same fixed ideal sampling coordinate frame. The use of very large scale intergrated circuits for memories and multiplier/accumulators results in a design with a processing.speed/power ratio in excess of 10**5 pixels per second per Watt and providing 1/16 pixel resampling accuracy.
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