A very high speed integrated circuit is required to perform a 3-pixel-by-3-pixel sliding window convolution over an image. To perform this on real-time video requires on the order of \frac{9 mult}{pixel} \times \frac{...
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A very high speed integrated circuit is required to perform a 3-pixel-by-3-pixel sliding window convolution over an image. To perform this on real-time video requires on the order of \frac{9 mult}{pixel} \times \frac{512^architecture pixels}{frame} or 71 × 10 6 multiplies/sec. A device has been designed to perform 90 × 10 6 multiply-accumulate operations/sec. using 8-bit input words and providing full precision output. Since the device can perform general vector multiplication, it is therefore useful for general digital filtering. Sets of devices may be used to increase accuracy or to chain together to form high-order FIR filters, This paper describes the algorithms and architecture used within the device.
Today, with large volumes of data, high throughput requirements, and more complex imageprocessing.algorithms, the emphasis is on interactive imageprocessing. Consequently, image displays are beginning to occupy a ce...
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Today, with large volumes of data, high throughput requirements, and more complex imageprocessing.algorithms, the emphasis is on interactive imageprocessing. Consequently, image displays are beginning to occupy a central role in imageprocessing.architectures. This paper presents some historical background on image displays and identifies the functional capabilities required in today's displays. Provided next is a summary of current image display architectures and system design philosophy. The paper concludes with a projection of technology and indicates what impact these technologies will have on future display systems.
This paper presents a degree of freedom or information content analysis of images in the context of digitalimageprocessing. As such it represents an attempt to quantify the number of truly independent samples one ga...
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This paper presents a degree of freedom or information content analysis of images in the context of digitalimageprocessing. As such it represents an attempt to quantify the number of truly independent samples one gathers with imaging devices. The degrees of freedom of a sampled image itself are developed as an approximation problem. Here, bicubic splines with variable knots are employed in an attempt to answer the question as to what extent images are finitely representable in the context of digital sensors and computers. Relatively simple algorithms for good knot placement are given and result in spline approximations that achieve significant parameter reductions at acceptable error levels. The knots themselves are shown to be useful as an indicator of image activity and have potential as an image segmentation device, as well as easy implementation in CCD signal processing.and focal plane smart sensor arrays. Both mathematical and experimental results are presented.","doi":"10.1109/TPAMI.1981.4767103","publicationTitle":"IEEE Transactions on Pattern Analysis and Machine Intelligence","startPage":"299","endPage":"310","rightsLink":"http://***/AppDispatchServlet?publisherName=ieee&publication=0162-8828&title=image+Approximation+by+Variable+Knot+Bicubic+Splines&isbn=&publicationDate=May+1981&author=Dennis+G.+Mccaughey&ContentID=10.1109/TPAMI.1981.4767103&orderBeanReset=true&startPage=299&endPage=310&volumeNum=PAMI-3&issueNum=3","displayPublicationTitle":"IEEE Transactions on Pattern Analysis and Machine Intelligence","pdfPath":"/iel5/34/4767093/***","keywords":[{"type":"IEEE Keywords","kwd":["Signal processing.algorithms","Sensor arrays","image analysis","Information analysis","digitalimages","image sensors","Computer errors","image segmentation","Charge coupled devices","Array signal processing.]},{"type":"Author Keywords ","kwd":["spline functions","Approximation theory","degrees of freedom","image approximation","imageprocessing.,"smart
Various aspects of software and hardware architectures of signal level imageprocessing.are described. First a brief survey is presented of data structures for signal level images and relationships between these struc...
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Various aspects of software and hardware architectures of signal level imageprocessing.are described. First a brief survey is presented of data structures for signal level images and relationships between these structures and imageprocessing.algorithms. Then architectures of imageprocessing.hardware are classified into four classes by giving representative examples of each class. Also the possibility is discussed of applying data flow architectures to the problem of signal level imageprocessing.
This study presents a systematic development of hierarchical, or tree-based, representations of digital pictures which have been proposed for use in computer graphics and imageprocessing. Starting with the one dimens...
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This study presents a systematic development of hierarchical, or tree-based, representations of digital pictures which have been proposed for use in computer graphics and imageprocessing. Starting with the one dimensional case, the development proceeds to quadtrees (the 2-D case), then to octrees (the 3-D case), and finally to hextrees (the 4-D case), and the relationships shown between successive representations. A brief summary of the algorithms and results for quadtress is presented. The details of an algorithm for projecting an octree onto a quadtree are presented;this algorithm is necessary for producing a display of an octree on an output device.
This study proposed the optimal processor interconnection topologies for parllel processing. The topologies are optimal with respect to the performance/cost ratio under the controlled message transfer delay and can be...
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This study proposed the optimal processor interconnection topologies for parllel processing. The topologies are optimal with respect to the performance/cost ratio under the controlled message transfer delay and can be systematically constructed for an arbitrary number of processors. The addition and the deletion of processors are simple and done with the minimum number of bus reconnections. The message transfer delay, as well as the reliability, can be controlled by changing the degree of the topology. Owing to these properties, the optimal interconnection topologies are suitable for many kinds of parallel processing.systems and algorithms.
VLSI technology has been rapidly driving down the cost per function of digital signal processing. Indeed, the functions being built today in one box or one rack using modern IC's would have been economically or ph...
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VLSI technology has been rapidly driving down the cost per function of digital signal processing. Indeed, the functions being built today in one box or one rack using modern IC's would have been economically or physically impossible just a few years ago (i.e. 300MHZ, 1 million point real time FFT). This same technology has opened the door to larger, more complex, algorithms to solve bigger problems--such as imageprocessing.or voice recognition. These newer algorithms require in some cases greater precision, but more often, greater dynamic range in the calculations than that possible with the older fixed point machines. This paper describes four VLSI circuits needed to drive down the cost of high speed floating point arithmetic.
Fast-Fourier-transform (FFT) algorithms increase the speed of digital-signal processing. The speed of the FFT operations can, in turn, be increased by using new computing components and techniques. Monolithic multipli...
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Fast-Fourier-transform (FFT) algorithms increase the speed of digital-signal processing. The speed of the FFT operations can, in turn, be increased by using new computing components and techniques. Monolithic multiplier-accumulators can calculate a product and sum within a single computer clock cycle (often in less than 100 ns). With a four-cycle butterfly operation in an ″in-place″ architecture, or with several such butterflies in a ″pipeline″ arrangement, the overall speed is extremely high. The computational element referred to as a ″butterfly″ is fundamental to the FFT. The basic butterfly operation combines two complex input points (X//n and Y//m) and delivers two complex output points (Y//n and Y//m). Four multiplications and six additions are required in a butterfly computation, and an N-point FFT requires (N/2) log//2N butterfly operations. Two special multiplier-accumulators can execute a so-called decimation-in-time in-place butterfly sequence in four computer cycles. Other sequences take from eight to 16 cycles with a single conventional multiplier, and up to nine cycles with two such multipliers.
The realization of a fast-Fourier transform (FFT) processor for realtime spectrum analysis of voice-band signals using a single chip signal processing.peripheral is described. The chip processes FFT algorithms to comp...
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The realization of a fast-Fourier transform (FFT) processor for realtime spectrum analysis of voice-band signals using a single chip signal processing.peripheral is described. The chip processes FFT algorithms to compute the discrete Fourier transform (DFT) of an N-point sequence by decomposing the sequence into shorter sequence DFT's. The chip is a 16 bit microcomputer with architecture and instruction set optimized for digital signal processing. It features a 12 × 12 bit parallel multiplier pipelined to operate in a single instruction cycle of 300nsec. Designed as a micro-processor peripheral it allows efficient partitioning of system tasks in performing a variety of signal processing.functions.
A new concept of designing multiprocessors, which share not only memory but also specially chosen peripheral processors and VLSI functional units, is introduced in this paper. Queuing analysis is performed on the pote...
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A new concept of designing multiprocessors, which share not only memory but also specially chosen peripheral processors and VLSI functional units, is introduced in this paper. Queuing analysis is performed on the potential throughput of the Purdue multiprocessor system (PUMPS). Configuration design of the shared resource pool is demonstrated with a special PUMPS design for interactive imageprocessing. The resource optimization techniques being developed can be also applied to configuration design of PUMPS for any other scientific applications.
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