This study presents a systematic development of hierarchical, or tree-based, representations of digital pictures which have been proposed for use in computer graphics and imageprocessing. Starting with the one dimens...
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This study presents a systematic development of hierarchical, or tree-based, representations of digital pictures which have been proposed for use in computer graphics and imageprocessing. Starting with the one dimensional case, the development proceeds to quadtrees (the 2-D case), then to octrees (the 3-D case), and finally to hextrees (the 4-D case), and the relationships shown between successive representations. A brief summary of the algorithms and results for quadtress is presented. The details of an algorithm for projecting an octree onto a quadtree are presented;this algorithm is necessary for producing a display of an octree on an output device.
This study proposed the optimal processor interconnection topologies for parllel processing. The topologies are optimal with respect to the performance/cost ratio under the controlled message transfer delay and can be...
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This study proposed the optimal processor interconnection topologies for parllel processing. The topologies are optimal with respect to the performance/cost ratio under the controlled message transfer delay and can be systematically constructed for an arbitrary number of processors. The addition and the deletion of processors are simple and done with the minimum number of bus reconnections. The message transfer delay, as well as the reliability, can be controlled by changing the degree of the topology. Owing to these properties, the optimal interconnection topologies are suitable for many kinds of parallel processing.systems and algorithms.
VLSI technology has been rapidly driving down the cost per function of digital signal processing. Indeed, the functions being built today in one box or one rack using modern IC's would have been economically or ph...
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VLSI technology has been rapidly driving down the cost per function of digital signal processing. Indeed, the functions being built today in one box or one rack using modern IC's would have been economically or physically impossible just a few years ago (i.e. 300MHZ, 1 million point real time FFT). This same technology has opened the door to larger, more complex, algorithms to solve bigger problems--such as imageprocessing.or voice recognition. These newer algorithms require in some cases greater precision, but more often, greater dynamic range in the calculations than that possible with the older fixed point machines. This paper describes four VLSI circuits needed to drive down the cost of high speed floating point arithmetic.
Fast-Fourier-transform (FFT) algorithms increase the speed of digital-signal processing. The speed of the FFT operations can, in turn, be increased by using new computing components and techniques. Monolithic multipli...
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Fast-Fourier-transform (FFT) algorithms increase the speed of digital-signal processing. The speed of the FFT operations can, in turn, be increased by using new computing components and techniques. Monolithic multiplier-accumulators can calculate a product and sum within a single computer clock cycle (often in less than 100 ns). With a four-cycle butterfly operation in an ″in-place″ architecture, or with several such butterflies in a ″pipeline″ arrangement, the overall speed is extremely high. The computational element referred to as a ″butterfly″ is fundamental to the FFT. The basic butterfly operation combines two complex input points (X//n and Y//m) and delivers two complex output points (Y//n and Y//m). Four multiplications and six additions are required in a butterfly computation, and an N-point FFT requires (N/2) log//2N butterfly operations. Two special multiplier-accumulators can execute a so-called decimation-in-time in-place butterfly sequence in four computer cycles. Other sequences take from eight to 16 cycles with a single conventional multiplier, and up to nine cycles with two such multipliers.
The realization of a fast-Fourier transform (FFT) processor for realtime spectrum analysis of voice-band signals using a single chip signal processing.peripheral is described. The chip processes FFT algorithms to comp...
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The realization of a fast-Fourier transform (FFT) processor for realtime spectrum analysis of voice-band signals using a single chip signal processing.peripheral is described. The chip processes FFT algorithms to compute the discrete Fourier transform (DFT) of an N-point sequence by decomposing the sequence into shorter sequence DFT's. The chip is a 16 bit microcomputer with architecture and instruction set optimized for digital signal processing. It features a 12 × 12 bit parallel multiplier pipelined to operate in a single instruction cycle of 300nsec. Designed as a micro-processor peripheral it allows efficient partitioning of system tasks in performing a variety of signal processing.functions.
A new concept of designing multiprocessors, which share not only memory but also specially chosen peripheral processors and VLSI functional units, is introduced in this paper. Queuing analysis is performed on the pote...
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A new concept of designing multiprocessors, which share not only memory but also specially chosen peripheral processors and VLSI functional units, is introduced in this paper. Queuing analysis is performed on the potential throughput of the Purdue multiprocessor system (PUMPS). Configuration design of the shared resource pool is demonstrated with a special PUMPS design for interactive imageprocessing. The resource optimization techniques being developed can be also applied to configuration design of PUMPS for any other scientific applications.
The advantages gained by applying microprocessor and LSI technologies in the broad spectrum of imageprocessing.hardware are printed out. image preprocessors and previously hardwired analyzers have gained intelligence...
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The advantages gained by applying microprocessor and LSI technologies in the broad spectrum of imageprocessing.hardware are printed out. image preprocessors and previously hardwired analyzers have gained intelligence. More advanced analyzers and general purpose image processors have become portable and less expensive. For high power image processors, it has now become feasible to build large arrays of processing.elements working in parallel. As an example of the use of microprocessors in the imageprocessing.field, the design considerations and the architecture of a multiprocessor autonomous imageprocessing.system are described.
Computational techniques involving contrast enhancement and noise filtering on two-dimensional image arrays are developed based on their local mean and variance. These algorithms are nonrecursive and do not require th...
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Computational techniques involving contrast enhancement and noise filtering on two-dimensional image arrays are developed based on their local mean and variance. These algorithms are nonrecursive and do not require the use of any kind of transform. They share the same characteristics in that each pixel is processed independently. Consequently, this approach has an obvious advantage when used in real-time digitalimageprocessing.applications and where a parallel processor can be used. For both the additive and multiplicative cases, the a priori mean and variance of each pixel is derived from its local mean and variance. Then, the minimum mean-square error estimator in its simplest form is applied to obtain the noise filtering algorithms. For multiplicative noise a statistical optimal linear approximation is made. Experimental results show that such an assumption yields a very effective filtering algorithm. Examples on images containing 256 × 256 pixels are given. Results show that in most cases the techniques developed in this paper are readily adaptable to real-time imageprocessing.
A description is given of an original technique of digital picture processing. which is particularly interesting by its versatility and its simplicity of implementation. This is due to the fact that the k-forms are me...
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A description is given of an original technique of digital picture processing. which is particularly interesting by its versatility and its simplicity of implementation. This is due to the fact that the k-forms are merely the codification of the local structural information in k given directions. This technic enables us to write new algorithms of edge detection, edge following and texture analysis. Also shown is the relation between k-forms (k greater than or equal to 2) operators.
A description is given of a special purpose processor for digital signal processing.applications. The main emphasis in the design of this processor has been a low cost/performance ratio, which can be improved even fur...
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A description is given of a special purpose processor for digital signal processing.applications. The main emphasis in the design of this processor has been a low cost/performance ratio, which can be improved even further by the use of Reduced Computational Complexity (RCC) algorithms to implement signal processing.kernels, such as DFT's and filters. This processor which is called the Research Signal Processor (RSP), has a single operand instruction format to permit ease of programming in the processor's own high level assembler language. The RSP very efficiently implements multiplications by constants, through the use of canonical signed digit representation of numbers, into shift and adds. One outstanding feature of the processor is the ability to handle asynchronous I/O and synchronous I/O under program control, this aspect is indeed crucial to most stand-along signal processing.applications.
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