A description is given of the design and construction of special electronic hardware for extracting higher level features, such as corners and holes, from a gray scale image. The processor has a parallel pipeline arch...
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A description is given of the design and construction of special electronic hardware for extracting higher level features, such as corners and holes, from a gray scale image. The processor has a parallel pipeline architecture so that the digital logic is utilized efficiently. Features of gradient direction histograms for all pixels in a 128 by 128 image using a 5 by 5 aperture can be computed in less than . 5 second, typically . 2 seconds. This compares favorably with a computation time of 50 to 55 seconds for a minicomputer using optimized code. Special processors aid the development of algorithms by giving humans the ability to get feedback quickly, following the adjustment of parameters. Industrial applications for high-speed image analysis hardware include the inspection, recognition and orientation of workpieces.
A description is given of a special purpose processor for digital signal processing.applications. The main emphasis in the design of this processor has been a low cost/performance ratio, which can be improved even fur...
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A description is given of a special purpose processor for digital signal processing.applications. The main emphasis in the design of this processor has been a low cost/performance ratio, which can be improved even further by the use of Reduced Computational Complexity (RCC) algorithms to implement signal processing.kernels, such as DFT's and filters. This processor which is called the Research Signal Processor (RSP), has a single operand instruction format to permit ease of programming in the processor's own high level assembler language. The RSP very efficiently implements multiplications by constants, through the use of canonical signed digit representation of numbers, into shift and adds. One outstanding feature of the processor is the ability to handle asynchronous I/O and synchronous I/O under program control, this aspect is indeed crucial to most stand-along signal processing.applications.
A description is given of an original technique of digital picture processing. which is particularly interesting by its versatility and its simplicity of implementation. This is due to the fact that the k-forms are me...
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A description is given of an original technique of digital picture processing. which is particularly interesting by its versatility and its simplicity of implementation. This is due to the fact that the k-forms are merely the codification of the local structural information in k given directions. This technic enables us to write new algorithms of edge detection, edge following and texture analysis. Also shown is the relation between k-forms (k greater than or equal to 2) operators.
An architecture for fault tolerance in a database management system is based upon the concepts of careful replacement and differential files on multiple media with backup copies available. An algorithm for transaction...
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A description is given of the design and construction of special electronic hardware for extracting higher level features, such as corners and holes, from a gray scale image. The processor has a parallel pipeline arch...
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A description is given of the design and construction of special electronic hardware for extracting higher level features, such as corners and holes, from a gray scale image. The processor has a parallel pipeline architecture so that the digital logic is utilized efficiently. Features of gradient direction histograms for all pixels in a 128 by 128 image using a 5 by 5 aperture can be computed in less than . 5 second, typically . 2 seconds. This compares favorably with a computation time of 50 to 55 seconds for a minicomputer using optimized code. Special processors aid the development of algorithms by giving humans the ability to get feedback quickly, following the adjustment of parameters. Industrial applications for high-speed image analysis hardware include the inspection, recognition and orientation of workpieces.
Orthogonal transforms such as the discrete Fourier transform and the discrete cosine transform (DCT) are useful for feature extraction, filtering and data compression in digitalimageprocessing. This report reviews r...
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Orthogonal transforms such as the discrete Fourier transform and the discrete cosine transform (DCT) are useful for feature extraction, filtering and data compression in digitalimageprocessing. This report reviews recent topics on fast algorithms for orthogonal transforms. First, discrete Fourier transforms based on fast convolution are discussed. The S. Winograd's Fourier transform algorithm (WFTA) is representative. The free-size fast Fourier transform algorithm and the DCT are also described. Next, attention is paid to such new techniques as the discrete linear base transform and the Alpha transform. Other topics related to transform techniques such as the number theoretic transform are also introduced. Finally, various 2-D transform algorithms are compared in terms of required computational time in a virtual-memory computer. It is shown that the previously proposed transform algorithm without transposing data matrix is a very efficient way to execute the 2-D orthogonal transform.
Microprocessors have achieved great popularity because they are inexpensive, convenient, and flexible. A microprocessor with an architecture chosen to efficiently perform digital signal processing.algorithms would ret...
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Microprocessors have achieved great popularity because they are inexpensive, convenient, and flexible. A microprocessor with an architecture chosen to efficiently perform digital signal processing.algorithms would retain these advantages when used to implement digital signal processing. One such architecture is the Research Signal Processor (RSP) which was designed by Abraham Peled and constructed at the IBM Thomas J. Watson Research Center. In order for the RSP to be cost effective, however, it must be capable of implementing a wide range of problems so that the cost of developing an LSI version can be borne by many applications. The potential applications, however, vary greatly in size. A microprocessor capable of implementing the largest of these applications would be expensive and underutilized for many others. The approach we have chosen is to implement modestly sized applications with a single RSP, and to distribute larger applications over several RSPs. In the hope of keeping the cost of this distribution small, two simple structures, the parallel and cascade clusters were first investigated. This paper presents the attributes of these structures when used to implement the FFT, FIR filters and IIR filters. The types of data transfers required to implement these algorithms are also found, and the I/O capabilities of the RSP chosen to perform these transfers are presented.
This paper describes a parallel high speed multiprocessor architecture suitable for realizing a 512×512 point 2-D FFT in under 1/30 of a second; enabling real time video display processing. The hardware employs a...
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This paper describes a parallel high speed multiprocessor architecture suitable for realizing a 512×512 point 2-D FFT in under 1/30 of a second; enabling real time video display processing. The hardware employs a constant geometry algorithm for the implementation and utilizes 16 butterfly processors. The machine can be described as a Multiple Instruction Multiple Data (MIMD) type of machine since 16 processors will be working on 16 sets of data simultaneously. The memory organization is modular in design and provides conflict-free access to all 16 processors at all times. The memory can be interfaced to a host computer which can do other nonreal time picture processing.operations on the transformed image.
Researchers in digitalimageprocessing.are appling fundamental mathematics to two-dimensional data to accomplish such endeavors as mathematical transforms of images, coding to allow image compression, image enhanceme...
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Researchers in digitalimageprocessing.are appling fundamental mathematics to two-dimensional data to accomplish such endeavors as mathematical transforms of images, coding to allow image compression, image enhancement, image restoration, and the study of image quality. digitalimageprocessing.has evolved to the point where extremely large dynamic range and high resolution are commonplace. The most significant aspect of the hardware technology is the new architecture, including, multiplexing of data channels, pipelining of processors, high-speed RAM (random access memory) chips, and very high resolution color shadow mask and monochrome monitors. The turnkey operation provided by firmware operating systems is the second most significant breakthrough in systems configuration. Historically, there have been five major imageprocessing.activities: 1. image coding projects, 2. image restoration and enhancement projects, 3. image data extraction projects, 4. image analysis projects, 5. imageprocessing.system projects.
The ILLIAC IV is a large scale, array processor. Based on programs written for the ILLIAC IV and several algorithmic studies for array architecture, a number of conclusions can be drawn about the suitability of the IL...
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The ILLIAC IV is a large scale, array processor. Based on programs written for the ILLIAC IV and several algorithmic studies for array architecture, a number of conclusions can be drawn about the suitability of the ILLIAC IV for imageprocessing. The major types of imageprocessing.algorithms considered are multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The major architectural features of the ILLIAC IV and the conclusions about their applicability to imageprocessing.(based on this sample) are summarized. The memory system of the ILLIAC IV consists of a small (128K 64-bit words) scratch-pad memory in the array elements and a larger (8 million word) high-performance drum memory. The 500 megabit per second transfer rate between the drum and scratch-pad has proven adequate, but the 40 millisecond latency has proven restrictive to imageprocessing.because of the small ratio of computing to data transfer. Each processing.element has the capability of performing eight 8-bit arithmetic operations, rather than one 64-bit operation, so the entire array can be viewed as 512 8-bit processors.
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