The ILLIAC IV is a large scale, array processor. Based on programs written for the ILLIAC IV and several algorithmic studies for array architecture, a number of conclusions can be drawn about the suitability of the IL...
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The ILLIAC IV is a large scale, array processor. Based on programs written for the ILLIAC IV and several algorithmic studies for array architecture, a number of conclusions can be drawn about the suitability of the ILLIAC IV for imageprocessing. The major types of imageprocessing.algorithms considered are multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The major architectural features of the ILLIAC IV and the conclusions about their applicability to imageprocessing.(based on this sample) are summarized. The memory system of the ILLIAC IV consists of a small (128K 64-bit words) scratch-pad memory in the array elements and a larger (8 million word) high-performance drum memory. The 500 megabit per second transfer rate between the drum and scratch-pad has proven adequate, but the 40 millisecond latency has proven restrictive to imageprocessing.because of the small ratio of computing to data transfer. Each processing.element has the capability of performing eight 8-bit arithmetic operations, rather than one 64-bit operation, so the entire array can be viewed as 512 8-bit processors.
Although many have proposed array processors as convenient and efficient devices for imageprocessing.and pattern recognition, the majority have either not extended their ideas as far as construction of an array, or h...
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Although many have proposed array processors as convenient and efficient devices for imageprocessing.and pattern recognition, the majority have either not extended their ideas as far as construction of an array, or have been referring only to a semi-parallel device in which data is pipe-lined through a small array of usually nine processors, so that the parallelism does not extend beyond the immediate neighbourhood of a single pixel. In CLIP4, however, the parallelism is extensive, there being one processor for every pixel in a 96 by 96 pixel image. The objective of this study is to review the CLIP4 imageprocessing.system from the point of view of the user and to discuss how imageprocessing.algorithms can be recast in order to take advantage of the unusual architecture.
Presented is the design of a flexible expandable multi-processor system for video graphics and imageprocessing. The design involves a central controller which broadcasts data to a variable number of independently exe...
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Applications of imageprocessing.to FLIR systems include image enhancement, to improve the imagery displayed to the observer and automatic target cueing, to reduce the operators search time. The Prototype Automatic Ta...
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This paper describes the features of a multimicroprocessor architecture for digital signal processing. The use of a multiport optical memory as a design component, along with the synchronous operation of the processor...
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This paper describes the features of a multimicroprocessor architecture for digital signal processing. The use of a multiport optical memory as a design component, along with the synchronous operation of the processors, allows particularly efficient implementation for one and two dimensional finite impulse response and infinite impulse response filters. This paper also describes an approach to the automatic generation of efficient code for the multi-microprocessor architecture being implemented for a class of linear DSP algorithms.
Programmable Logic Arrays (PLA's) are digital electronic devices capable of performing complex logic functions at very high rates - up to 20 million operations per second. They are available in many configurations...
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Programmable Logic Arrays (PLA's) are digital electronic devices capable of performing complex logic functions at very high rates - up to 20 million operations per second. They are available in many configurations including several types that can be field programmed using simple and inexpensive equipment. They are thus ideal devices for implementing several types of video rate imageprocessing.algorithms, particularly those algorithms that involve a high degree of adaptability or binary decision making. A description is given of the technology and operation of PLA's and several representative imageprocessing.applications are detailed, including an adaptive differential signal compression algorithm, a gradient generator, and an edge continuity detector.
Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware ...
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Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware currently available in the commercial market and describes several experimental imageprocessing.systems exhibiting a number of unique features. A new integrated display/processor architecture is also suggested which, when compared to existing systems, offers considerably enhanced performance without substantial increases in hardware complexity. This approach features a memory-centered design in which a multiported memory is shared between the processor and display, memory is interleaved using skewed storage techniques, and dynamic reconfiguration of the memory and interface is provided. The advantages of this architecture over the standard computer plus add-on display for operations such as image compression, multispectral classification, digital filtering, and image display are described.
This paper describes the architecture of a medium scale digitalimageprocessing.system developed as a research tool for analysis of meteorological data. The system is also being used for research on efficient image p...
This paper describes the architecture of a medium scale digitalimageprocessing.system developed as a research tool for analysis of meteorological data. The system is also being used for research on efficient imageprocessing.systems. Four qualitative performance measures for any image processor are introduced with specific application to the present machine. Preliminary results with noise reduction algorithms in satellite data are presented. Lastly, the versatility of the machine as a test bed for architectural studies of the computational structure of image processors with a microprogrammable control unit is discussed.
With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presente...
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With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presented in this paper can be used in real-time applications of microprocessors. The data were obtained with a class of backward difference digital differential analyzers - BDDDA's based on multi-step predictor integration formulas. Optimized coefficient and transfer increment word lengths are given, in the sense that quantization and quadrature errors can be balanced. A register level organization of the integrating architecture is proposed with a natural 'crescendo' of complexity for higher orders of integration. A practical design example is discussed.
Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating loc...
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Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating location and direction of scan head can be superimposed on the image. It has linear measurement calipers. Moreover, it is entirely versatile as far as on line or off line imageprocessing.is concerned because any kind of algorithms can be fed to a RAM via CANAK to achieve the desired processing.
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