This paper describes the features of a multimicroprocessor architecture for digital signal processing. The use of a multiport optical memory as a design component, along with the synchronous operation of the processor...
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This paper describes the features of a multimicroprocessor architecture for digital signal processing. The use of a multiport optical memory as a design component, along with the synchronous operation of the processors, allows particularly efficient implementation for one and two dimensional finite impulse response and infinite impulse response filters. This paper also describes an approach to the automatic generation of efficient code for the multi-microprocessor architecture being implemented for a class of linear DSP algorithms.
Programmable Logic Arrays (PLA's) are digital electronic devices capable of performing complex logic functions at very high rates - up to 20 million operations per second. They are available in many configurations...
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Programmable Logic Arrays (PLA's) are digital electronic devices capable of performing complex logic functions at very high rates - up to 20 million operations per second. They are available in many configurations including several types that can be field programmed using simple and inexpensive equipment. They are thus ideal devices for implementing several types of video rate imageprocessing.algorithms, particularly those algorithms that involve a high degree of adaptability or binary decision making. A description is given of the technology and operation of PLA's and several representative imageprocessing.applications are detailed, including an adaptive differential signal compression algorithm, a gradient generator, and an edge continuity detector.
Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware ...
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Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware currently available in the commercial market and describes several experimental imageprocessing.systems exhibiting a number of unique features. A new integrated display/processor architecture is also suggested which, when compared to existing systems, offers considerably enhanced performance without substantial increases in hardware complexity. This approach features a memory-centered design in which a multiported memory is shared between the processor and display, memory is interleaved using skewed storage techniques, and dynamic reconfiguration of the memory and interface is provided. The advantages of this architecture over the standard computer plus add-on display for operations such as image compression, multispectral classification, digital filtering, and image display are described.
This paper describes the architecture of a medium scale digitalimageprocessing.system developed as a research tool for analysis of meteorological data. The system is also being used for research on efficient image p...
This paper describes the architecture of a medium scale digitalimageprocessing.system developed as a research tool for analysis of meteorological data. The system is also being used for research on efficient imageprocessing.systems. Four qualitative performance measures for any image processor are introduced with specific application to the present machine. Preliminary results with noise reduction algorithms in satellite data are presented. Lastly, the versatility of the machine as a test bed for architectural studies of the computational structure of image processors with a microprogrammable control unit is discussed.
With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presente...
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With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presented in this paper can be used in real-time applications of microprocessors. The data were obtained with a class of backward difference digital differential analyzers - BDDDA's based on multi-step predictor integration formulas. Optimized coefficient and transfer increment word lengths are given, in the sense that quantization and quadrature errors can be balanced. A register level organization of the integrating architecture is proposed with a natural 'crescendo' of complexity for higher orders of integration. A practical design example is discussed.
Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating loc...
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Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating location and direction of scan head can be superimposed on the image. It has linear measurement calipers. Moreover, it is entirely versatile as far as on line or off line imageprocessing.is concerned because any kind of algorithms can be fed to a RAM via CANAK to achieve the desired processing.
Banded Toeplitz matrices of large size occur in many practical problems [1]-[6]. Here the problem of inversion as well as the problem of solving simultaneous equations of the type Hx = y, when H is a large banded Toep...
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Banded Toeplitz matrices of large size occur in many practical problems [1]-[6]. Here the problem of inversion as well as the problem of solving simultaneous equations of the type Hx = y, when H is a large banded Toeplitz matrix, are considered. It is shown via certain circular decompositions of H that such equations may be exactly solved in O(N \log_algorithms N) rather than in O(N 2 ) computations as in Levinson-Trench algorithms. Furthermore, the algorithms of this paper are nonrecursive (as compared to the Levinson-Trench algorithms), and afford parallel processor architectures and others such as transversal filters [17] where the computation time becomes proportional to N rather than to N \log N . Finally, a principle of matrix decomposition for fast inversion of matrices is introduced as a generalization of the philosophy of this paper.
Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware ...
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Computer-based imageprocessing.and display capabilities can be provided by many different architectures with varying degrees of efficiency and complexity. This paper provides a survey of the capabilities of hardware currently available in the commercial market and describes several experimental imageprocessing.systems exhibiting a number of unique features. A new integrated display/processor architecture is also suggested which, when compared to existing systems, offers considerably enhanced performance without substantial increases in hardware complexity. This approach features a memory-centered design in which a multiported memory is shared between the processor and display, memory is interleaved using skewed storage techniques, and dynamic reconfiguration of the memory and interface is provided. The advantages of this architecture over the standard computer plus add-on display for operations such as image compression, multispectral classification, digital filtering, and image display are described.
Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating loc...
详细信息
Some of the advantages obtained with a microprocessor based ultrasound imaging system are discussed. The system described can do B mode imaging, it can store M mode with depth marks, and a vector cursor indicating location and direction of scan head can be superimposed on the image. It has linear measurement calipers. Moreover, it is entirely versatile as far as on line or off line imageprocessing.is concerned because any kind of algorithms can be fed to a RAM via CANAK to achieve the desired processing.
With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presente...
详细信息
With the advent of microprocessors and their matched, integrated peripheral devices, the digital implementation of complex algorithms, with different degrees of parallelism, has become attractive. The results presented in this paper can be used in real-time applications of microprocessors. The data were obtained with a class of backward difference digital differential analyzers - BDDDA's based on multi-step predictor integration formulas. Optimized coefficient and transfer increment word lengths are given, in the sense that quantization and quadrature errors can be balanced. A register level organization of the integrating architecture is proposed with a natural 'crescendo' of complexity for higher orders of integration. A practical design example is discussed.
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