The field of image manipulation is dynamic, exploiting a range of algorithms to analyze, manipulate and enhance digitalimages. Our study focuses on a crucial application of imageprocessing, which is the elimination ...
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ISBN:
(纸本)9783031821523;9783031821530
The field of image manipulation is dynamic, exploiting a range of algorithms to analyze, manipulate and enhance digitalimages. Our study focuses on a crucial application of imageprocessing, which is the elimination of blind Gaussian noise in order to improve image quality and facilitate image analysis by preserving essential details. In this research, we explore the use of different convolutional neural network (CNN) architectures to tackle the problem of blind Gaussian noise, applying different noise levels, ranging from low to high. We present an in-depth comparative analysis of the three main CNN architectures: DnCNN, DRNet and RIDNet, highlighting the quantitative and qualitative experimental results of these different approaches. These methods have demonstrated remarkable performance in imageprocessing tasks, particularly denoising, using various techniques built into CNNs, such as batch normalization and residual learning. Our results show that these techniques bring significant improvements to all three CNN approaches, as evidenced by the remarkable performance observed in the experimental results. These findings underline the robustness of CNN architectures in the face of complex noise scenarios, such as the blind noise scenario addressed in our study.
This paper presents a novel image encryption algorithm that leverages the chaotic properties of the Chen system, the cryptographic strength of OpenSSL, and the mathematical robustness of the Fibonacci Q-Matrix. The pr...
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With the aim of retrieving high-quality images from corrupted versions, image restoration meets the extensive demand of application scenarios. State-of-the-art methods solve this problem by means of designing convolut...
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With the aim of retrieving high-quality images from corrupted versions, image restoration meets the extensive demand of application scenarios. State-of-the-art methods solve this problem by means of designing convolution blocks in multistage architectures. However, the existing methods blindly extract and fuse features without considering which parts of the features are more effective for image restoration. In this paper, we propose a significance-wise mechanism with the goal of identifying the importance degree of each region in the feature representation and providing crucial feature information. Through the calculation of nonlinear function in the significance-wise mechanism, the region which is more conducive to image restoration will get higher importance values. Two important types of information are generated within the attention mechanism, including: (i) feature-sufficient maps with abundant feature representations, and (ii) significance-wise maps with the importance degree of patch information in the corrupted images. With the coordination of feature-sufficient maps and significance-wise maps, the network architecture can focus higher attention on crucial parts of feature information. Furthermore, we design a multistage feature fusion block with the significance-wise mechanism. Compared with existing attention mechanisms, our significance-wise mechanism has the ability to identify and generate crucial feature representation for multiple image restoration tasks. Due to the novel design of the network, we successfully implement multiple restoration tasks only by fine-tuning the number of channels once on a network. Abundant quantitative and qualitative experiments demonstrate that the effective image restoration network (EIRN) outperforms existing state-of-the-art algorithms on eleven datasets across a series of image restoration tasks, including image deblurring, denoising, super-resolution, and deraining. The source code and pretrained models will be availa
The paper discusses the features of solving a class of problems for pattern recognition using the STM-32 microcontroller. The problem of pattern recognition can be solved on neural networks of different architectures,...
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Present paper is a continuation of works on evaluation of red, green, blue (RGB) to hue, saturation, intensity (HSI) colour space transformation in regard to digitalimageprocessing application in optical measurement...
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Present paper is a continuation of works on evaluation of red, green, blue (RGB) to hue, saturation, intensity (HSI) colour space transformation in regard to digitalimageprocessing application in optical measurements methods. HSI colour space seems to be the roost suitable domain for engineering applications due to its immunity to non-ii n i form lightning. Previous stages referred to the analysis of various RGB to HSI colour space transformations equivalence and programming platform configuration influence on the algorithms execution. The main purpose of this step is to understand the influence of computer processor architecture on the computing time, since analysis of images requires considerable computer resources. The technical development of computer components is very fast and selection of particular processor architecture can be an advantage for fastening the image analysis and then the measurements results. In this paper the colour space transformation algorithms, their complexity and execution time are discussed. The roost common algorithms were compared with the authors own one. Computing time was considered as the main criterion taking into account a technical advancement of two computer processor architectures. It was shown that proposed algorithm was characterized by shorter execution time than in reported previously results.
The proceedings contain 35 papers. The topics discussed include: error resilience in nano-electronic digital circuits and systems;thermal camera cores - present and future;application of evolutionary algorithm to sign...
ISBN:
(纸本)9788362065233
The proceedings contain 35 papers. The topics discussed include: error resilience in nano-electronic digital circuits and systems;thermal camera cores - present and future;application of evolutionary algorithm to signal analysis in frequency domain;implementation of a fixed-point 2D Gaussian filter for imageprocessing based on FPGA;a centerline-based algorithm for estimation of blood vessels radii from 3D raster images;the renal vessel segmentation for facilitation of partial nephrectomy;robustness analysis of automatic speech signal recognition system against factors degrading speech signal;voice pathologies identification - speech signals, features and classifiers evaluation;simple object coordination tracking based on background modeling;complexity reduced turbo differential decoding based on layered LDPC decoding;a hybrid relaying protocol for wireless cooperative networks based on the log-likelihood ratio;and application of auto calibration and linearization algorithms to improve sound quality of computer devices.
The discrete cosine transform (DCT) is a central mathematical operation in several digital signal processing methods and image/video standards. In this paper, we propose a collection of twelve approximations for the 8...
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The discrete cosine transform (DCT) is a central mathematical operation in several digital signal processing methods and image/video standards. In this paper, we propose a collection of twelve approximations for the 8-point DCT based on integer functions. Considered functions include: the floor, ceiling, truncation, and rounding-off functions. Sought approximations are required to meet the following specific criteria: (i) very low arithmetic complexity, (ii) orthogonality or quasi-orthogonality, and (iii) low-complexity inversion. By varying a scaling parameter, approximations could be systematically obtained and several existing approximations were identified as particular cases of the proposed methodology. Particular cases include the signed DCT and the rounded DCT. Four new quasi-orthogonal approximations were introduced and their practical relevance was demonstrated. All approximations were given fast algorithms based on matrix factorization methods. Proposed approximations are multiplierless;their computation requires only additions and bit-shifting operations. Additive complexity ranged from 18 to 24 additions. Obtained approximations were compared with the exact DCT and assessed in the context of JPEG-like image compression. As quality assessment measures, we considered the peak signal-to-noise ratio and the structural similarity index. Because its low-complexity and good performance properties, the proposed approximations are suitable for hardware implementation in dedicated architectures. (C) 2013 Elsevier B.V. All rights reserved.
Matrix inversion is a computationally intensive basic block of many digital signal processingalgorithms. To decrease the cost of their implementations, programmers often prefer the fixed-point arithmetic. This arithm...
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ISBN:
(纸本)9791092279061
Matrix inversion is a computationally intensive basic block of many digital signal processingalgorithms. To decrease the cost of their implementations, programmers often prefer the fixed-point arithmetic. This arithmetic requires less resources and runs faster than the floating-point arithmetic, but all the arithmetical details must be handled by the programmer. In this article, we overcome this drawback by presenting an automated approach to synthesize fixed-point code for matrix inversion based on Cholesky decomposition. First we rigorously define the square root and division operators especially in terms of rounding error, and we implement them in the CGPE library. This allows us to provide accuracy certificates for the generated code. Second we propose a workflow based on Cholesky decomposition that carefully uses these operators to produce accurate code for the basic blocks of matrix inversion. Finally we illustrate the efficiency of our approach on some benchmarks, and show how it allows us to synthesize accurate code in a few seconds and thus to reduce the development time of fixed-point matrix inversion.
image and video compression plays a major role in multimedia transmission. Specifically the discrete cosine transform (DCT) is the key tool employed in a vast variety of compression standards such as H.265/HEVC due to...
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ISBN:
(纸本)9781628410266
image and video compression plays a major role in multimedia transmission. Specifically the discrete cosine transform (DCT) is the key tool employed in a vast variety of compression standards such as H.265/HEVC due to its remarkable energy compaction properties. Rapid growth in digital imaging applications, such as multimedia and automatic surveillance that operates with limited bandwidths has led to extensive development of video processing systems. The main objective of this paper is to discuss some DCT approximations equipped with fast algorithms which require minimum addition operations and zero multipliers or bit-shifting operations leading to significant reductions in chip area and power consumption compared to conventional DCT algorithms. We provide complete design details for several k x k, k = 8, 16 blocked 2-D algorithms for DCT computation with video evaluation using HEVC software encoder. Custom digitalarchitectures are proposed, simulated and implemented on Xilinx FPGAs and verified in conjunction with software models.
This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore digital Signal Processor (DSP) at runtime. This RTOS ...
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This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore digital Signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. The RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. The platform used for this demonstration is a Texas Instruments Keystone ii Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory subsystem, Multicore Navigator and multiple dedicated accelerators.
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