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Conference on Design and architectures for Signal and image processing

作者： Matthieu Martel Amine Najahi Guillaume Revy LIRMM Univ. Montpellier II Montpellier France DALI Univ. Perpignan Via Domitia Perpignan France CNRS LIRMM Montpellier France

Matrix inversion is a computationally intensive basic block of many digital signal processing algorithms. To decrease the cost of their implementations, programmers often prefer the fixed-point arithmetic. This arithmetic requires less resources and runs faster than the floating-point arithmetic, but all the arithmetical details must be handled by the programmer. In this article, we overcome this drawback by presenting an automated approach to synthesize fixed-point code for matrix inversion based on Cholesky decomposition. First we rigorously define the square root and division operators especially in terms of rounding error, and we implement them in the CGPE library. This allows us to provide accuracy certificates for the generated code. Second we propose a workflow based on Cholesky decomposition that carefully uses these operators to produce accurate code for the basic blocks of matrix inversion. Finally we illustrate the efficiency of our approach on some benchmarks, and show how it allows us to synthesize accurate code in a few seconds and thus to reduce the development time of fixed-point matrix inversion.

关键词： Matrix decomposition Accuracy digital signal processing Symmetric matrices Algorithm design and analysis

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A secure OsiriX plug-in for detecting suspicious lesions in breast DCE-MRI

A secure OsiriX plug-in for detecting suspicious lesions in ...

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13th International Conference on algorithms and architectures for Parallel processing, ICA3PP 2013

作者： Piantadosi, Gabriele Marrone, Stefano Sansone, Mario Sansone, Carlo University of Naples Federico II Italy

ISBN: (纸本)9783319038889

Up-to-date medical image processing is currently based on very sophisticated algorithms that often require a large computational load not always available on conventional workstations. Moreover, algorithms are in continuous evolution and hence clinicians are typically required to update their workstation periodically. The main objective of this paper is to propose a secure and versatile client-server architecture for providing these services at a low cost. In particular, we developed a plug-in allowing OsiriX - a widespread medical image processing application dedicated to DICOM images coming from several equipments - to interact with a system for automatic detection of suspicious lesions in breast DCE-MRI. The large amount of data and the privacy of the information flowing through the network requires a flexible but comprehensive security approach. According to NIST guidelines, in our proposal data are transmitted over SSL/TLS channel after an authentication and authorization procedure based on X.509 standard digital certificate associated with a 3072bit RSA Key Pair. Authentication and authorization procedure is achieved through the services offered by Java JAAS classes. © Springer International Publishing Switzerland 2013.

关键词： Big data

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Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

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IET COMPUTERS AND digital TECHNIQUES 2010年第2期4卷 126-142页

作者： Sudarsanam, A. Barnes, R. Carver, J. Kallam, R. Dasu, A. Utah State Univ ECE Dept Logan UT 84322 USA

Field programmable gate arrays (FPGAs) are increasingly being adopted as the primary on-board computing system for autonomous deep space vehicles. There is a need to support several complex applications for navigation and image processing in a rapidly responsive on-board FPGA-based computer. Developing such a computer requires the designer to explore and combine several design concepts such as systolic array (SA) design, hardware-software partitioning and partial dynamic reconfiguration (PDR). In this study a microprocessor/co-processor design that can simultaneously accelerate multiple single precision floating-point algorithms is proposed. Two such algorithms are extended Kalman filter (EKF) and discrete wavelet transform (DWT). Key contributions include (i) polymorphic systolic array (PolySA), comprising partial reconfigurable regions that can accelerate algorithms amenable to being mapped onto linear SAs and (ii) performance model to predict the overall execution time of EKF algorithm on the proposed PolySA architecture. When implemented on a low-end Xilinx Virtex4 SX35 FPGA, the design provides a speed-up of at least 4.18x and 6.61x over a state-of-the-art microprocessor used in spacecraft systems for the EKF and DWT algorithms, respectively. The performance of EKF algorithm on the proposed PolySA architecture was compared against the performance on two types of conventional (non-polymorphic) hardware architectures and the results showed that the proposed architecture outperformed the other two architectures in most of the test cases.

关键词： image processing autonomous deep space vehicles spacecraft systems navigation partial dynamic reconfiguration polymorphic systolic array accelerators design hardware architectures Kalman filters space vehicles Integral transforms performance model PolySA architecture discrete wavelet transform algorithms multiple single precision floating-point algorithms General aspects of aircraft, space vehicles and satellites on-board computing system EKF algorithm discrete wavelet transforms Logic circuits extended Kalman filter systolic array accelerators design field programmable gate arrays DWT Filters and other networks systolic arrays on-board FPGA-based computer state-of-the-art microprocessor hardware-software partitioning Xilinx Virtex4 SX35 FPGA microprocessor/co-processor design PDR particle accelerators

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ACE16k based stand-alone system for real-time pre-processing tasks

ACE16k based stand-alone system for real-time pre-processing...

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Conference on VLSI Circuits and Systems ii

作者： Carranza, L Jiménez-Garrido, F Liñán-Cembrano, G Roca, E Meana, SE Rodríguez-Vázquez, A CSIC CNM Inst Microelect Sevilla Seville 41012 Spain

ISBN: (纸本)0819458325

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

关键词： ACE 16k vision system stand-alone vision pre-processing real-time full custom control unit

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Residue Number System's (RNS) Non-modular Operations Efficient Implementation Based on Chinese Remainder Theorem ii (CRT ii)

Residue Number System's (RNS) Non-modular Operations Efficie...

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作者： Al-Radadi, Eid Ayad Wayne State University

学位级别：Ph.D.

Residue number system (RNS) is an alternative method of number representation, it is basically different from weighted number system such as decimal and binary. The RNS is based on modular arithmetic. The RNS system has attracted many researchers in the last decade. The researchers have been focused on the theory of improving the RNS system and applying the RNS in some application areas, such as digital signal processing, fast fourier transform (FFT), digital filter, and image processing. The RNS system is inherently parallel, modular, and fault isolating. In addition, the main advantage of RNS system is the carry free operation in modular arithmetic operation: addition, subtraction, and multiplication. On the other hand, in non-modular operation such as, magnitude comparison, sign detection, and overflow detection are very slow and time consuming. Therefore, the RNS system is not widely used. Also the implementation of the RNS algorithms require efficient modular adders, and modular multipliers. This dissertation presents algorithms and implementation techniques that improve the RNS non-modular operations. New methods are proposed for sign detection, RNS to Binary and Binary to RNS converters, number comparison, and overflow detection. These methods are based on chinese remainder theorem ii (CRT ii). Also in this dissertation new design architectures for modulo 2n-a adders and modulo 2n-a multipliers are presented, where a = 1 or 2m + 1 and m < n.

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Parallelization and performance of 3D ultrasound imaging beamforming algorithms on modern clusters

Parallelization and performance of 3D ultrasound imaging bea...

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Conference Proceedings of the 2002 International Conference on Supercomputing

作者： Zhang, Fan Bilas, A. Dhanantwari, Amar Plataniotis, Kostas N. Abiprojo, Robert Stergiopoulos, Stergios Dept. of Electrical and Comp. Eng. University of Toronto 10 King's College Road Toronto Ont. M5S3G4 Canada

Recently there has been a lot of interest in improving the infrastructure used in medical applications. In particular, there is renewed interest on non-invasive, high-resolution diagnostic methods. One such method is digital, 3D ultrasound medical imaging. Current state-of-the-art ultrasound systems use specialized hardware for performing advanced processing of input data to improve the quality of the generated images. Such systems are limited in their capabilities by the underlying computing architecture and they tend to be expensive due to the specialized nature of the solutions they employ. Our goal in this work is twofold: (i) To understand the behavior of this class of emerging medical applications in order to provide an efficient parallel implementation and (ii) to introduce a new benchmark for parallel computer architectures from a novel and important class of applications. We address the limitations faced by modern ultrasound systems by investigating how all processing required by advanced beamforming algorithms can be performed on modern clusters of high-end PCs connected with low-latency, high-bandwidth system area networks. We investigate the computational characteristics of a state-of-the-art algorithm and demonstrate that today's commodity architectures are capable of providing almost-real-time performance without compromising image quality significantly.

关键词： Parallel processing systems

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Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power

Dynamically parameterized algorithms and architectures to ex...

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IEEE International Conference on Acoustics, Speech, and Signal processing

作者： Burleson, W Tessier, R Goeckel, D Swaminathan, S Jain, P Euh, J Venkatraman, S Thyagarajan, V Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)0780370414

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power consumption. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper examines five parameterized computations which are typically implemented in hardware for a wireless multimedia terminal: 1) motion estimation, 2) discrete cosine transform, 3) Lempel-Ziv lossless compression, 4) 3D graphics light rendering and 5) Viterbi decoding, Each computation is examined for the capability of dynamically adapting the algorithm and architecture parameters to variations in their respective input signals. Dynamically reconfigurable low-power implementations of each computation are currently underway.

关键词： digital signal processing

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Variable partitioning for dual memory bank DSPs

Variable partitioning for dual memory bank DSPs

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IEEE International Conference on Acoustics, Speech, and Signal processing

作者： Leupers, R Kotte, D Univ Dortmund Dept Comp Sci 12 D-44221 Dortmund Germany

ISBN: (纸本)0780370414

DSPs with dual memory banks offer high memory bandwidth, which is required for high-performance applications. However, such DSP architectures pose problems for C compilers, which are mostly not capable of partitioning program variables between memory banks. As a consequence, time-consuming assembly programming is required for an efficient coding of time-critical algorithms. This paper presents a new technique for automatic variable partitioning between memory banks in compilers, which leads to a higher utilization of available memory bandwidth in the generated machine code. We present experimental results obtained by integrating the proposed technique into an existing C compiler for the AMS Gepard, an industrial DSP core.

关键词： digital signal processing

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A unified design framework for Vector Rotational CORDIC Family based on Angle Quantization process

A unified design framework for Vector Rotational CORDIC Fami...

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IEEE International Conference on Acoustics, Speech, and Signal processing

作者： Wu, AY Wu, CS Natl Taiwan Univ Dept Elect Engn Taipei 106 Taiwan

ISBN: (纸本)0780370414

Vector rotation is the key operation employed extensively in many digital signal processing applications. In this paper, we introduce a new design concept called Angle Quantization (AQ). It can be used as a design index for vector rotational operation, where the rotational angle is known in advance. Based on the AQ process, we establish a unified design framework for cost-effective low-latency rotational algorithms and architectures. Several existing works, such as conventional CORDIC, AR-CORDIC, MVR-CORDIC, and EEAS-based CORDIC, can be fitted into the design framework, forming a Vector Rotational CORDIC Family. Based on the new design framework, we can realize high-speed / low-complexity rotational VLSI circuits, whereas without degrading the precision performance in fixed-point implementations.

关键词： digital signal processing

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A VLSI architecture of 2D wavelet transforms

A VLSI architecture of 2D wavelet transforms

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7th IEEE International Conference on Electronics, Circuits and Systems

作者： Achour, C Houle, JL Davidson, J Ecole Polytech Montreal PQ H3C 3A7 Canada

ISBN: (纸本)0780365429

This paper presents a new implementation of a 2D wavelet transform in a VLSI circuit, for real-time digital signal processing. The parallel algorithm of the 2D wavelet transform (2D-WT) used for designing and implementing this new architecture enhances the performance of computations. The proposed multi-elementary processor architecture of 2D-WT yields a very flexible hardware configuration. This approach offers a high processing speed, relative to other methods, for providing the wavelet coefficients. The 2D-WT is a powerful tool for several applications, the most important one being image processing.

关键词： algorithms architectures Fourier transform FPGA Processor VLSI Wavelet transforms

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