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architectures and algorithms for digital image processing ii 1985

作者： Reader, Cliff Searing, S. Skubic, J. Vasquez, M. Weiner, L. Bose, G. International Imaging Systems 1500 Buckeye Drive MilpitasCA95035-7484 United States

The architecture is based upon a general, flexible core together with modular functional subunits. Configurations can address a wide range of applications and budgets. At one extreme we can configure a system to support a single user who roams at a real-time speed across an 8kx8k pixel image, performing real-time interactive warping and large kernel convolution on a lkxlk displayed image. At the other extreme, eight users can be working at dedicated workstations performing simple functions continuously, and occasionally performing a warp or convolution. Alternatively, a configuration with no display at all can be dedicated at a receiving station to registering images to latitude/longitude coordinate space, and correcting for radiometric nonlinearity in the sensor. We hope this will be a very utilitarian machine. © 1985 SPIE. All rights reserved.

关键词： Convolution

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The design of video processor in TV tracking system 2

The design of video processor in TV tracking system

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architectures and algorithms for digital image processing ii 1985

作者： Wen, C.S. Chang, O. Chiang, S.M. Department of Electrical Engineering Chung Cheng Institute of Technology Taoyuan335 Taiwan

In multifunctional video tracking system, a number of specific factors must be considered in the presence of noises to the video signal in order to increase video processing capability for all-weather automatic video control. In fact, since the contrast of the video responses in accordance with different background environments, the signal threshold level and video gain adjustment must be reciprocally considered in a manner for keeping an optimal video source to the processor. In this paper, an adaptive video processor is implemented for all-weather conditions with respect to the auto-threshold control and the auto-gain control. This particular design structure utilizes the different pre-selection table stored in ROM which is in accordance with the practical contrast and brightness variations to provide an optimal video signal to the tracking system. © 1985 SPIE. All rights reserved.

关键词： Video signal processing

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Modular real time architectures for image understanding applications 2

Modular real time architectures for image understanding appl...

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architectures and algorithms for digital image processing ii 1985

作者： Wehner, William W. Signal and Image Processing Group Systems and Research Center 2600 Ridgway Parkway N.E. MN17-2306 MinneapolisMN55413 United States

Diverse image understanding (IU) system applications and attendant reduced life cycle cost requirements call for real time system architectures which are increasingly flexible, maintainable, reprogrammable, and upgradable. The requirements for algorithm mapping to architecture are sufficiently complex to require automated functional analysis tools. Algorithm complexity dictates higher order language (HOL) system programmability for acceptable software development cycles. Architecture complexity requires automated architecture simulation/emulation support for acceptable hardware development cycles. Honeywell, through external contracts and IR&D, is pursuing the definition and development of real time IU architectures (and algorithms) which cost-effectively support diverse applications including tactical targeting and reconnaissance, scene analysis, robot vision, and autonomous navigation. We are addressing the systems requirements of these applications with designs which are modular, expandable, and software configurable. Our presentation will overview the IU applications we are pursuing, our architectural approach to meeting system real time throughput requirements, and our underlying design methodology for architecture development. © 1985 SPIE. All rights reserved.

关键词： Real time systems

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Multilevel architectures for image processing

Multilevel architectures for Image Processing

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architectures and algorithms for digital image processing iiI 1985

作者： Basille, Jean-Luc Castan, Serge Laboratoire CERFIA Université Paul Sabatier 118 route de Narbonne Toulouse Cedex31062 France

Among all the numerous parallel structures that have been studied for and involved in image processing, this article gives some elements for an answer to the problem of the choice of some architectures dedicated to Im... 详细信息

关键词： image processing

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Advanced digital video processing unit

Advanced digital video processing unit

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architectures and algorithms for digital image processing ii 1985

作者： Orbach, Z. Hershman, A. ELBIT Ground Weapon Systems Division Advanced Technology Center Haifa31053 Israel

Following the development of several high-speed image processing systems, it has been acknowledged that the only way to achieve real low power and system compactness is by using customized ICs. In an effort to reduce the development cost and the turnaround time, a unique architecture has been devised to combine semicustom ICs and off-the-shelf devices. The unit is controlled by a microprocessor. The microprocessor sets the various parameters according to the desired process. The procedure itself is carried out by a miniarray processor composed of an Address Generator IC, off the shelf static RAMs, and a Data processing IC. Using advanced CMOS technology and pipeline architecture, high-speed processing is achieved while power consumption and system volum are kept very low. The paper presents the architecture of the unit along with various configurations in which it can be used, and its performance. © 1985 SPIE. All rights reserved.

关键词： Video signal processing

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Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

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IET COMPUTERS AND digital TECHNIQUES 2010年第2期4卷 126-142页

作者： Sudarsanam, A. Barnes, R. Carver, J. Kallam, R. Dasu, A. Utah State Univ ECE Dept Logan UT 84322 USA

Field programmable gate arrays (FPGAs) are increasingly being adopted as the primary on-board computing system for autonomous deep space vehicles. There is a need to support several complex applications for navigation and image processing in a rapidly responsive on-board FPGA-based computer. Developing such a computer requires the designer to explore and combine several design concepts such as systolic array (SA) design, hardware-software partitioning and partial dynamic reconfiguration (PDR). In this study a microprocessor/co-processor design that can simultaneously accelerate multiple single precision floating-point algorithms is proposed. Two such algorithms are extended Kalman filter (EKF) and discrete wavelet transform (DWT). Key contributions include (i) polymorphic systolic array (PolySA), comprising partial reconfigurable regions that can accelerate algorithms amenable to being mapped onto linear SAs and (ii) performance model to predict the overall execution time of EKF algorithm on the proposed PolySA architecture. When implemented on a low-end Xilinx Virtex4 SX35 FPGA, the design provides a speed-up of at least 4.18x and 6.61x over a state-of-the-art microprocessor used in spacecraft systems for the EKF and DWT algorithms, respectively. The performance of EKF algorithm on the proposed PolySA architecture was compared against the performance on two types of conventional (non-polymorphic) hardware architectures and the results showed that the proposed architecture outperformed the other two architectures in most of the test cases.

关键词： image processing autonomous deep space vehicles spacecraft systems navigation partial dynamic reconfiguration polymorphic systolic array accelerators design hardware architectures Kalman filters space vehicles Integral transforms performance model PolySA architecture discrete wavelet transform algorithms multiple single precision floating-point algorithms General aspects of aircraft, space vehicles and satellites on-board computing system EKF algorithm discrete wavelet transforms Logic circuits extended Kalman filter systolic array accelerators design field programmable gate arrays DWT Filters and other networks systolic arrays on-board FPGA-based computer state-of-the-art microprocessor hardware-software partitioning Xilinx Virtex4 SX35 FPGA microprocessor/co-processor design PDR particle accelerators

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RELAXED LOOK-AHEAD PIPELINED LMS ADAPTIVE FILTERS AND THEIR APPLICATION TO ADPCM CODER

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS ii-ANALOG AND digital SIGNAL processing 1993年第12期40卷 753-766页

作者： SHANBHAG, NR PARHI, KK UNIV MINNESOTA DEPT ELECT ENGNMINNEAPOLISMN 55455

The relaxed look-ahead technique is presented as an attractive technique for pipelining adaptive filters. Unlike conventional look-ahead, the relaxed look-ahead does not attempt to maintain the input-output mapping between the serial and pipelined architectures but preserves the adaptation characteristics. The use of this technique results in a small hardware overhead which would not be possible with conventional look-ahead. The relaxed look-ahead is employed to develop fine-grained pipelined architectures for least mean-squared (LMS) adaptive filtering. Convergence analysis results are presented for the pipelined architecture. The proposed architecture achieves the desired speed-up with marginal or no degradation in the convergence behavior. Past work in pipelined transversal LMS filtering are shown to be special cases of this architecture. Simulation results verifying the convergence analysis results for the pipelined LMS filter are presented. The pipelined LMS filter is then employed to develop a high-speed adaptive differential pulse-code-modulation (ADPCM) codec. The new architecture has a negligible hardware overhead which is independent of the number of quantizer levels, the predictor order and the pipelining level. Additionally, the pipelined codec has a much lower output latency than the level of pipelining. Theoretical analysis indicates that the Output signal-to-noise ratio (SNR) is degraded with increase in speed-up. Simulations with image data indicate that speed-ups of up to 44 can be achieved with less than 1 dB loss in SNR.

关键词： Least squares approximation Adaptive filters Pipeline processing digital signal processing Signal processing algorithms Convergence Transversal filters Filtering Hardware Degradation

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A dualistic model to describe computer architectures

A dualistic model to describe computer architectures

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architectures and algorithms for digital image processing ii 1985

作者： Nitezki, Peter Engel, Michael Forschungszentrum Informatik an der Universität Karlsruhe Haid- und Neu-Str. 10-14 Karlsruhe 1D-7500 Germany

The Dualistic Model for Computer Architecture Description uses a hierarchy of abstraction levels to describe a computer in arbitrary steps of refinement from the top of the user interface to the bottom of the gate level. In our Dualistic Model the description of an architecture may be divided into two major parts called "Concept" and "Realization". The Concept of an architecture on each level of the hierarchy is an Abstract Data Type that describes the functionality of the computer and an implementation of that data type relative to the data type of the next lower level of abstraction. The Realization on each level comprises a language describing the means of user interaction with the machine, and a processor interpreting this language in terms of the language of the lower level. The surface of each hierarchical level, the data type and the language express the behaviour of a machine at this level, whereas the implementation and the processor describe the structure of the algorithms and the system. In this model the Principle of Operation maps the object and computational structure of the Concept onto the structures of the Realization. Describing a system in terms of the Dualistic Model is therefore a process of refinement starting at a mere description of behaviour and ending at a description of structure. This model has proven to be a very valuable tool in exploiting the parallelism in a problem and it is very transparent in discovering the points where parallelism is lost in a special architecture. It has successfully been used in a project on a survey of Computer Architecture for image processing and Pattern Analysis in Germany. © 1985 SPIE. All rights reserved.

关键词： Computer architecture

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Locating objects in a complex image

Locating objects in a complex image

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architectures and algorithms for digital image processing ii 1985

作者： Dawson, Ben Treese, George Natural Computation Group Massachusetts Institute of Technology E10-120 79 Amherst St. CambridgeMA02139 United States

A vision machine must locate possible objects before it can identify them. In simple images, where the objects and illumination are known, locating possible objects can be part of, and secondary to, identification. In complex, natural images it is more efficient to use a quick and simple method to locate possible objects first, and then to selectively identify them. This parallels the strategy normally used by the human visual system. We present a theory for how possible objects, called "blobs", will be represented in an image, and explore some measures of importance for these candidate objects. An example algorithm based on this theory can quickly generate a list of possible object locations for the identification computation. We discuss the implementation of this example algorithm on a standard image processing system. © 1985 SPIE. All rights reserved.

关键词： Location

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System design for local neighborhood processing

System design for local neighborhood processing

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architectures and algorithms for digital image processing ii 1985

作者： Leonard, Patrick F. Mudge, Trevor N. Synthetic Vision Systems Inc. 3744 Plaza Drive Ann ArborMI48104 United States Electrical Engineering and Computer Science Department University of Michigan Ann ArborMI48109 United States

A class of processors which perform local neighborhood or cellular operations has well-documented applications in image processing. The architectural feature which unites these processors is their use of special-purpose hardware to compute image transformations based both on the values and on the spatial relationship of pixels in the input image. Typical operations include 3×3 convolution and mathematical morphology. processing elements which compute cellular operations have been incorporated in a variety of system architectures. These range from single-processor, recirculating buffer systems to systems which have thousands of processors in a four-way interconnected mesh. Another feature which unites these processors is that they operate on images in the iconic domain. A new class of non-iconic processor is introduced here which uses image encoding schemes to reduce the number of operations required for certain classes of operations by between one and two orders of magnitude. © 1985 SPIE. All rights reserved.

关键词： Mathematical morphology

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