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检索条件"任意字段=Architectures and Algorithms for Digital Image Processing II 1985"

共 77 条记录，以下是51-60 订阅

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Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power

Dynamically parameterized algorithms and architectures to ex...

引用

IEEE International Conference on Acoustics, Speech, and Signal processing

作者： Burleson, W Tessier, R Goeckel, D Swaminathan, S Jain, P Euh, J Venkatraman, S Thyagarajan, V Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)0780370414

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power consumption. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper examines five parameterized computations which are typically implemented in hardware for a wireless multimedia terminal: 1) motion estimation, 2) discrete cosine transform, 3) Lempel-Ziv lossless compression, 4) 3D graphics light rendering and 5) Viterbi decoding, Each computation is examined for the capability of dynamically adapting the algorithm and architecture parameters to variations in their respective input signals. Dynamically reconfigurable low-power implementations of each computation are currently underway.

关键词： digital signal processing

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IMPLEMENTING A PARALLEL CONNECTED COMPONENT ALGORITHM ON MIMD architectures.

IMPLEMENTING A PARALLEL CONNECTED COMPONENT ALGORITHM ON MIM...

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1985 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and image Database Management.

作者： Hummel, Robert Rojer, Alan Courant Inst of Mathematical Sciences New York Univ NY USA Courant Inst of Mathematical Sciences New York Univ NY USA

ISBN: (纸本)0818606622

The choice of an appropriate architecture for parallel image processing can have a large impact on the efficiency and the ease of implementation of vision algorithms. A shared-memory MIMD architecture may be effective for higher-level algorithms that require nonlocal communication between image elements. In such a machine, processor allocation and synchronization are key issues. Techniques are presented for allocation and synchronization of processors in the New York University Ultracomputer, using the fetch-and-add primitive. This scheme is applied to implement a parallel connected-component algorithm. It is concluded that the method allows a high degree of parallelism with relative ease of programming.

关键词： COMPUTER SYSTEMS, digital

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Low-complexity multiplierless DCT approximations for low-power HEVC digital IP cores

Low-complexity multiplierless DCT approximations for low-pow...

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Geospatial InfoFusion and Video Analytics IV and Motion imagery for ISR and Situational Awareness ii

作者： Kulasekera, Sunera C. Madanayake, Arjuna Cintra, Renato J. Bayer, Fabio M. Potluri, Uma Univ Akron Dept Elect Engn Akron OH 44325 USA Univ Fed Pernambuco Dept Estatist Recife PE Brazil Univ Fed Santa Maria Dept Estatist Santa Maria RS Brazil Univ Fed Santa Maria LACESM Santa Maria RS Brazil

ISBN: (纸本)9781628410266

image and video compression plays a major role in multimedia transmission. Specifically the discrete cosine transform (DCT) is the key tool employed in a vast variety of compression standards such as H.265/HEVC due to its remarkable energy compaction properties. Rapid growth in digital imaging applications, such as multimedia and automatic surveillance that operates with limited bandwidths has led to extensive development of video processing systems. The main objective of this paper is to discuss some DCT approximations equipped with fast algorithms which require minimum addition operations and zero multipliers or bit-shifting operations leading to significant reductions in chip area and power consumption compared to conventional DCT algorithms. We provide complete design details for several k x k, k = 8, 16 blocked 2-D algorithms for DCT computation with video evaluation using HEVC software encoder. Custom digital architectures are proposed, simulated and implemented on Xilinx FPGAs and verified in conjunction with software models.

关键词： Approximate DCT fast algorithms HEVC FPGA

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Signal processing - algorithms, architectures, Arrangements, and Applications Conference Proceedings, SPA

Signal Processing - Algorithms, Architectures, Arrangements,...

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19th IEEE Signal processing algorithms, architectures, Arrangements, and Applications Conference, SPA 2015

ISBN: (纸本)9788362065233

The proceedings contain 35 papers. The topics discussed include: error resilience in nano-electronic digital circuits and systems;thermal camera cores - present and future;application of evolutionary algorithm to signal analysis in frequency domain;implementation of a fixed-point 2D Gaussian filter for image processing based on FPGA;a centerline-based algorithm for estimation of blood vessels radii from 3D raster images;the renal vessel segmentation for facilitation of partial nephrectomy;robustness analysis of automatic speech signal recognition system against factors degrading speech signal;voice pathologies identification - speech signals, features and classifiers evaluation;simple object coordination tracking based on background modeling;complexity reduced turbo differential decoding based on layered LDPC decoding;a hybrid relaying protocol for wireless cooperative networks based on the log-likelihood ratio;and application of auto calibration and linearization algorithms to improve sound quality of computer devices.

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Residue Number System's (RNS) Non-modular Operations Efficient Implementation Based on Chinese Remainder Theorem ii (CRT ii)

Residue Number System's (RNS) Non-modular Operations Efficie...

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作者： Al-Radadi, Eid Ayad Wayne State University

学位级别：Ph.D.

Residue number system (RNS) is an alternative method of number representation, it is basically different from weighted number system such as decimal and binary. The RNS is based on modular arithmetic. The RNS system has attracted many researchers in the last decade. The researchers have been focused on the theory of improving the RNS system and applying the RNS in some application areas, such as digital signal processing, fast fourier transform (FFT), digital filter, and image processing. The RNS system is inherently parallel, modular, and fault isolating. In addition, the main advantage of RNS system is the carry free operation in modular arithmetic operation: addition, subtraction, and multiplication. On the other hand, in non-modular operation such as, magnitude comparison, sign detection, and overflow detection are very slow and time consuming. Therefore, the RNS system is not widely used. Also the implementation of the RNS algorithms require efficient modular adders, and modular multipliers. This dissertation presents algorithms and implementation techniques that improve the RNS non-modular operations. New methods are proposed for sign detection, RNS to Binary and Binary to RNS converters, number comparison, and overflow detection. These methods are based on chinese remainder theorem ii (CRT ii). Also in this dissertation new design architectures for modulo 2n-a adders and modulo 2n-a multipliers are presented, where a = 1 or 2m + 1 and m < n.

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image processing by a local-SIMD co-processor

Image processing by a local-SIMD co-processor

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architectures and algorithms for digital image processing iiI 1985

作者： Pachowicz, P.W. Institute for Control Systems Engineering and Telecommunication Academy of Mining and Metallurgy al.Mickiewicza 30 Cracow30-059 Poland

The idea of a co-processor to process distributed or marked local image data is described, The architecture, format of instruction and time effects for some algorithms are pointed out. Time effects for image processing by the co-processor can be obtained from 8 to 60 times faster than for the sequential computing by a single microprocessor. The application of the microprocessor - image co-processor unit makes one's way towards industrial picture processing and analysis of binary images, grey-level images, two types of images between themselves and moving pictures as well. © 1986 SPIE. All rights reserved.

关键词： Binary images

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image Encryption Based on Chen Chaotic System, OpenSSL S-Box and the Fibonacci Q-Matrix 27

Image Encryption Based on Chen Chaotic System, OpenSSL S-Box...

引用

27th IEEE Signal processing: algorithms, architectures, Arrangements, and Applications, SPA 2024

作者： Lotfy, Rana Gabr, Mohamed Mamdouh, Eyad Aboshousha, Amr Alexan, Wassim El-Damak, Dina Fathy, Abdallah Mansour, Marvy Badr Monir German University in Cairo Faculty of MET Cairo Egypt German University in Cairo Physics Department Cairo Egypt German University in Cairo Faculty of IET Cairo Egypt ElSewedy University of Technology - Polytechnic of Egypt Faculty of Engineering Technology Department of Electronic Engineering Technology Cairo Egypt The British University in Egypt Faculty of Engineering Department of Electrical Engineering Cairo Egypt

ISBN: (纸本)9788362065486

This paper presents a novel image encryption algorithm that leverages the chaotic properties of the Chen system, the cryptographic strength of OpenSSL, and the mathematical robustness of the Fibonacci Q-Matrix. The proposed method begins by generating an encryption key using the Chen chaotic system, known for its sensitivity to initial conditions and complex dynamic behavior. This key is then utilized in conjunction with a substitution box (S box) generated through OpenSSL to introduce non-linearity and diffusion into the encryption process. To further enhance security, the resulting image data undergoes a series of multiplications by a large number of Fibonacci Q-Matrices, exploiting their recursive properties for added complexity and confusion. Numerical results demonstrate the proposed algorithm's superior performance in terms of security and efficiency, making it a promising solution for safeguarding digital images against unauthorized access and cryptographic attacks. © 2024 Division of Signal processing and Electronic Systems, Poznan University of Technology (DSPES PUT).

关键词： Encryption algorithms

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ON APPLICATIONS OF MULTI-COLORED POLYGONAL MASKS AND THEIR COMPUTATION IN image processing PIPELINE architectures.

ON APPLICATIONS OF MULTI-COLORED POLYGONAL MASKS AND THEIR C...

引用

1985 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and image Database Management.

作者： Petkovic, D. Sanz, J. Dinstein, I. IBM Research Lab San Jose CA USA IBM Research Lab San Jose CA USA

ISBN: (纸本)0818606622

The authors describe efficient ways of computing digital multicolor polygonal masks in general-purpose pipeline processors and then present their applications in typical digital visual inspection tasks. Polygonal color mask computation is based on efficient computation of coordinate-reference gray-level images (ramps) and other simple general-purpose architectural features such as pixel-by-pixel logical operations and lookup tables. These procedures are highly parallel and can be efficiently implemented in pipeline processors. In addition, some parallel hardware can dramatically increase the efficiency of implementation. Applications of these color masks are discussed, namely, position-dependent segmentation and computation of accurate pixel or object position with respect to user-defined zones. The proposed algorithms offer accuracy, efficiency in pipeline processors, and flexibility. They are also attractive for software-based implementation.

关键词： COMPUTER SYSTEMS, digital

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Region algorithms to evaluate parallel vision architectures

Region algorithms to evaluate parallel vision architectures

引用

Applications of digital image processing XViiI

作者： Bonnin, Patrick J. Pissaloux, Edwige Univ. Paris XIII and ETCA Arcueil Cedex Fr

ISBN: (纸本)0819419230

The research presented here focuses on the general problem of finding tools and methods to compare and evaluate parallel architectures in this particular field: the computer vision. As there are several different parallel architectures proposed for machine vision, some means of comparison between them are necessary in order to employ the most suitable architecture for a given application. 'Benchmarks' are the most popular tools for machine speed comparison, but do not give any information on the most convenient hardware structures for implementation of a given vision problem. This paper tries to overcome this weakness by proposing a definition of the concept of a tool for the evaluation of parallel architecture (more general than a benchmark), and provides a characterization of the chosen algorithms. Taken into account different ways to process data, it is necessary to consider two different classes of machines: MISD and (MIMD, SPMD, SIMD) offering different programming models, thus leading to two classes of algorithms. Consequently, two algorithms, one for each class are proposed: 1) the extraction of connected components, and 2) a parallel region growing algorithm with data reorganization. The second algorithm tests the capabilities of the architecture to support the following: i) pyramidal data structures (initial region step), ii) a merge procedure between global and global information (adjacent regions to the growing region), and iii) a parallel merge procedure between local and global information (adjacent points to the growing region).

关键词： Parallel processing systems

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ALGORITHMIC COMPLEXITY, SPEED AND ARCHITECTURAL PARALLELISM IN LOW DATA-RATE VISUAL COMMUNICATION.

ALGORITHMIC COMPLEXITY, SPEED AND ARCHITECTURAL PARALLELISM ...

引用

digital processing of Signals in Communications.

作者： Martinex, K. Pearson, D.E. Univ of Essex Dep of Electrical Engineering Science Colchester Engl Univ of Essex Dep of Electrical Engineering Science Colchester Engl

ISBN: (纸本)0903748592

Consideration is given to the trade-off between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on an MC68000 processor indicated the need for a high degree of parallelism in order to meet the requirements of real-time, moving-picture data rates. However, insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables.

关键词： image processing

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