A vision machine must locate possible objects before it can identify them. In simple images, where the objects and illumination are known, locating possible objects can be part of, and secondary to, identification. In...
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Multiple-detector scanning systems exhibit striping patterns caused by non-uniform calibration and analog-to-digital quantization process. Traditional nonlinear destriping is based on cumulative histogram normalizatio...
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The parallel processing, high-speed, compact system fabrication possibility, low power dissipation and size, plus weight advantages of optical processors have achieved great strides in recent years. The architectures,...
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Out of all possible multiprocessor interconnection schemes, the time-shared bus has some advantages for hardware realisations. Not only is it one of the simpliest and cheapest ways to tie processors together, but it i...
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The discrete Hartley transform (DHT) and its fast algorithm were introduced recently. One of the advantages of the DHT is that the forward and inverse transforms are of the same form except for a normalization constan...
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The choice of an appropriate architecture for parallel imageprocessing can have a large impact on the efficiency and the ease of implementation of vision algorithms. A shared-memory MIMD architecture may be effective...
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ISBN:
(纸本)0818606622
The choice of an appropriate architecture for parallel imageprocessing can have a large impact on the efficiency and the ease of implementation of vision algorithms. A shared-memory MIMD architecture may be effective for higher-level algorithms that require nonlocal communication between image elements. In such a machine, processor allocation and synchronization are key issues. Techniques are presented for allocation and synchronization of processors in the New York University Ultracomputer, using the fetch-and-add primitive. This scheme is applied to implement a parallel connected-component algorithm. It is concluded that the method allows a high degree of parallelism with relative ease of programming.
The authors describe efficient ways of computing digital multicolor polygonal masks in general-purpose pipeline processors and then present their applications in typical digital visual inspection tasks. Polygonal colo...
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ISBN:
(纸本)0818606622
The authors describe efficient ways of computing digital multicolor polygonal masks in general-purpose pipeline processors and then present their applications in typical digital visual inspection tasks. Polygonal color mask computation is based on efficient computation of coordinate-reference gray-level images (ramps) and other simple general-purpose architectural features such as pixel-by-pixel logical operations and lookup tables. These procedures are highly parallel and can be efficiently implemented in pipeline processors. In addition, some parallel hardware can dramatically increase the efficiency of implementation. Applications of these color masks are discussed, namely, position-dependent segmentation and computation of accurate pixel or object position with respect to user-defined zones. The proposed algorithms offer accuracy, efficiency in pipeline processors, and flexibility. They are also attractive for software-based implementation.
作者：
Martinex, K.Pearson, D.E.Univ of Essex
Dep of Electrical Engineering Science Colchester Engl Univ of Essex Dep of Electrical Engineering Science Colchester Engl
Consideration is given to the trade-off between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on a...
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ISBN:
(纸本)0903748592
Consideration is given to the trade-off between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on an MC68000 processor indicated the need for a high degree of parallelism in order to meet the requirements of real-time, moving-picture data rates. However, insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables.
We consider an implementation of a class of SIMD parallel algorithms, referred to as a simple SIMD, onto systolic arrays, which have been considered as one candidate for VLSI-based cellular computers. The class of sim...
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ISBN:
(纸本)0444876626
We consider an implementation of a class of SIMD parallel algorithms, referred to as a simple SIMD, onto systolic arrays, which have been considered as one candidate for VLSI-based cellular computers. The class of simple SIMD algorithms are large enough to include many conventional SIMD algorithms, such as sorting, imageprocessing, and graph algorithms. We develop several time-efficient simulations of simple SIMD machines, which have global data communications, by systolic arrays with only local data communications. The systolic simulation theorems enable us to use any simple SIMD algorithms on the VLSI systolic arrays almost without much loss of time efficiency.
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