Having two, or more, transistors with different values of f T and BV CEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricati...
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Having two, or more, transistors with different values of f T and BV CEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricating these transistors on the same wafer is another important factor. Three different approaches for co-integrating high-performance and high-breakdown SiGe npn HBTs with minimal process deviation are presented herein. The work features a high-performance HBT with f T × BV CEO product of 500GHz-V and a high-breakdown HBT with over 430GHz-V integrated on the same wafer with one-mask deviation.
This paper addresses the integration of a new generation of high-speed SiGe HBTs with f T / f max of 300/500 GHz and minimum CML ring oscillator gate delays of 2.0 ps in a 0.13 μm bicmostechnology. Technological me...
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This paper addresses the integration of a new generation of high-speed SiGe HBTs with f T / f max of 300/500 GHz and minimum CML ring oscillator gate delays of 2.0 ps in a 0.13 μm bicmostechnology. Technological measures for improving the speed of the HBTs compared to our first 0.13 μm bicmos generation are discussed. These include scaling of lateral device dimensions and doping profiles as well as a reduced thermal budget and reduced salicide resistance.
The proceedings contain 60 papers. The topics discussed include: an ultra low Power 10 Gbps LVDS output driver;a SiGe bicmos operational amplifier with 48dB of gain and 9GHz unity gain bandwidth;a 37nV/sqrtHz 2.5V ref...
ISBN:
(纸本)9781424427260
The proceedings contain 60 papers. The topics discussed include: an ultra low Power 10 Gbps LVDS output driver;a SiGe bicmos operational amplifier with 48dB of gain and 9GHz unity gain bandwidth;a 37nV/sqrtHz 2.5V reference based on dual-threshold JFET technology;a 4-40MHz continuous-time LPF with on-chip automatic tuning for a direct conversion DBS tuner;a low power multi-mode baseband for direct-conversion WLAN transceiver and DVB-H;on the profile design of SiGe HBTs for RF lunar applications down to 43 K;gate controlled vertical-lateral NPN bipolar transistor in 90nm RFCMOS process;special RF/microwave devices in silicon-on-glass technology;forced-IE pinch-in maximum output voltage limit in SiGe HBTs operating at cryogenic temperatures;and digital control power - the key to intelligent power efficiency.
An optimum vertical SiGe SCR design is presented for on-chip electrostatic discharge (ESD) protection. The device response to fast transients, emulating ESD CDM-type events, is compared with standard clamp structures ...
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ISBN:
(纸本)9781612841663
An optimum vertical SiGe SCR design is presented for on-chip electrostatic discharge (ESD) protection. The device response to fast transients, emulating ESD CDM-type events, is compared with standard clamp structures having similar footprint-area, loading-capacitance and current handling ability. SCR designs include variation in the device's anode construction, anode geometry and triggering mechanism.
Isolated LDMOS transistors with thin gate oxides and good RF performance are key components in integrated RF circuits where large voltage shifts are required for the circuit functionality. We demonstrate the modular i...
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ISBN:
(纸本)9781612841663
Isolated LDMOS transistors with thin gate oxides and good RF performance are key components in integrated RF circuits where large voltage shifts are required for the circuit functionality. We demonstrate the modular integration of isolated NLDMOS and PLDMOS focusing on maximal RF performance into an advanced industrial 0.25 mu m SiGe:C bicmos process. A boundary condition for device construction was a limit for maximum deep n-well implantation energy of 750keV. The achieved values BVDSS/f(T)/f(MAX) of -21V/10GHz/35GHz for the PLDMOS and 16V/30GHz/53GHz for the isolated NLDMOS, respectively, reflect the excellent RF performance obtained.
Using time sampled DC measurements from standard bench-top semiconductor parameter analyzers, it proves possible to characterize low frequency noise of BJT's down to sub-mHz frequencies. The new technique is exemp...
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ISBN:
(纸本)9781612841663
Using time sampled DC measurements from standard bench-top semiconductor parameter analyzers, it proves possible to characterize low frequency noise of BJT's down to sub-mHz frequencies. The new technique is exemplified using SiGeC HBT's. Base current random telegraph noise with time constants of as long as tens of seconds is demonstrated.
The accurate measurement of power and other attributes of signals used in communications systems has become a necessary aspect in optimizing power consumption and data throughput. From simple portable, battery-powered...
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ISBN:
(纸本)9781612841663
The accurate measurement of power and other attributes of signals used in communications systems has become a necessary aspect in optimizing power consumption and data throughput. From simple portable, battery-powered devices to large scale base-stations and routers, knowledge of the signal characteristics and its environment enables the system to reconfigure itself and allocate power and bandwidth as needed. A combination of high-speed silicon-based process technologies and an unrelenting focus on precision circuit design have enabled the in-situ analog signal processing of signals to be performed accurately and practically non-invasively. A review of numerous signal measurement techniques developed at Analog Devices reveals an unusual combination of high-speed and precision design techniques.
determination methods for the emitter resistance of bipolar transistors are reviewed and evaluated with respect to the constraints introduced by modern SiGe:C HBT processes with f(MAX) reaching 500GHz [1]. Maximum tra...
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ISBN:
(纸本)9781612841663
determination methods for the emitter resistance of bipolar transistors are reviewed and evaluated with respect to the constraints introduced by modern SiGe:C HBT processes with f(MAX) reaching 500GHz [1]. Maximum transistor performance is obtained at ever higher current densities, involving huge self-heating effect which dramatically degrades the accuracy of existing methods. A new parameter extraction procedure is presented and compared to existing solutions. Finally, a simple methodology to correct self-heating effects is proposed, which advantageously increases the accuracy of emitter resistance determination under high self-heating conditions.
Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and...
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ISBN:
(纸本)9781612841663
Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and to limit the electric field across the intrinsic base-collector junction. This is accomplished by the transistor layout i.e. the mask design. Transistors with BVCEO = 12.6 V, V-A = 301 V and f(T) = 12.7 GHz are fabricated in a standard HCBT bicmos process flow without the use of the additional lithography masks. Physical behavior of the transistor is thoroughly examined by 3D device simulations.
A new SiGe bicmos process, SBC18H3 is described which features SiGe HBTs with 240GHz F-T and 270 GHz F-MAX. The HBT devices are described in detail along with several other mm-wave components included in the process. ...
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ISBN:
(纸本)9781612841663
A new SiGe bicmos process, SBC18H3 is described which features SiGe HBTs with 240GHz F-T and 270 GHz F-MAX. The HBT devices are described in detail along with several other mm-wave components included in the process. The process is based on a high-volume manufacturing-proven 0.18um SiGe bicmos base platform which has been running at TowerJazz for almost a decade and has been used to produce over 100,000 8" wafers. Additional mm-wave enablement devices offered in the process include MOS varactors, P-I-N diodes and sub-10fF MIM capacitors. Additional key metrics for the SiGe HBT device include an NFMIN of 2dB at 40GHz, a BVCEO of 1.6V and a DC current gain of 1200.
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