A Q-band class-B power amplifier implemented in a 0.13 μm SiGe bicmos process is presented. At 45 GHz, the PA achieves a 17.5 dBm saturated output power, a 16.6 dB peak power gain, and a 26% peak power-added efficien...
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A Q-band class-B power amplifier implemented in a 0.13 μm SiGe bicmos process is presented. At 45 GHz, the PA achieves a 17.5 dBm saturated output power, a 16.6 dB peak power gain, and a 26% peak power-added efficiency (PAE) with a 2.5V supply. A 2-stage, single-ended, inductor matched topology is used. To support envelope modulation transceiver topologies, the output common-emitter stage is optimized for high efficiency under varying supply voltage and maintains a peak PAE of greater than 21% throughout the supply voltage range of 1.3V to 2.5V. The PA occupies a total die area of 0.2 mm 2 .
A low cost / low power bicmos Ku-band down-converter IC with integrated LO-PLL for satellite TV is presented. The down-converter section shows 43dB conversion gain, with 6.5dB noise figure and output IP3 of 16dBm. The...
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A low cost / low power bicmos Ku-band down-converter IC with integrated LO-PLL for satellite TV is presented. The down-converter section shows 43dB conversion gain, with 6.5dB noise figure and output IP3 of 16dBm. The LO-PLL section achieves state-of-art integrated phase noise performance of 1° rms. The down-converter operates from the 5V supply commonly available in satellite TV outdoor units. Its current consumption of 52mA is to our knowledge the lowest ever reported for a similar function.
An approach to integrate extended high voltage (EHV) npn SiGe heterojunction bipolar transitors (HBTs) in a high-performance bicmos process is presented. The EHV HBTs are based on a dedicated high-energy implanted pho...
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An approach to integrate extended high voltage (EHV) npn SiGe heterojunction bipolar transitors (HBTs) in a high-performance bicmos process is presented. The EHV HBTs are based on a dedicated high-energy implanted phosphorus-doped subcollector. The epitaxially buried arsenic-doped subcollector of the conventional low-voltage (LV) and high-voltage (HV) HBTs, as well as the base-emitter configuration, which is shared between all three HBT types (i.e. LV, HV, and EHV), remains unchanged. The EHV devices that were fabricated are characterized by BV CE0 = 3.5 - 7.7 V, BV CB0 = 14 - 24 V, and peak-f T = 54 - 22 GHz. These figures of merit are tunable across the specified ranges by the subcollector implantation energy and dose. The integration of EHV HBTs in NXP's high-performance QUBiC4Xi process enables highly integrated transmitter and receiver ICs for microwave and millimeter-wave applications.
This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circ...
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This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-added-efficiency (PAE) of 38% at its 1 dB compression point (P 1dB ) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4-5% at ≥4 dB back-off from its P 1dB . This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions.
A three-stage, 77/79GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-bicmos. Common-base stages maximize output voltage swing and power, while a cascode first stage enhances gain for g...
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A three-stage, 77/79GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-bicmos. Common-base stages maximize output voltage swing and power, while a cascode first stage enhances gain for greater power-added efficiency (PAE). A frequency-scalable, parasitic-compensated balun combines power from the output stages to the 50Ω load with 2 area on-chip. The measured peak small-signal gain is 27dB at 83GHz, and -3dB bandwidth is >;8GHz. Maximum output power and peak-PAE are 18dBm and 9%, respectively, at 84GHz. The 0.23mm 2 active area PA consumes 395mW from a 2.5V supply.
High speed channel (HSC) resistive sensor interface is an analog sampling channel designed for measuring the resistance variations with data rate at 5 kHz. It measures the external resistance variation and digitizes t...
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High speed channel (HSC) resistive sensor interface is an analog sampling channel designed for measuring the resistance variations with data rate at 5 kHz. It measures the external resistance variation and digitizes the received signal using a 12-bit analog to digital converter (ADC). The HSC includes a Wheatstone bridge with programmable configurations, a high voltage cap stack sampler, a 6 th order Butterworth switching capacitor filter, and a continuous time variable gain amplifier (VGA). An 8-bit voltage mode calibration digital to analog converter (DAC) is used to calibrate the common mode voltage level. An 8-bit current mode stimulus DAC is used to provide the current source to the Wheatstone bridge through a high voltage current mirror. With radiation hardening by design (RHBD), the HSC is implemented in a 0.5 μm SiGe bicmostechnology for applications in aerospace environment under extreme temperature, radiation, pressure and vibration.
The proceedings contain 56 papers. The topics discussed include: a zero-second-IF SiGe bicmos satellite radio tuner using a single PLL for both and IF LO generation and a replica ring-VCO calibrated IF Filter;high spe...
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ISBN:
(纸本)9781424410194
The proceedings contain 56 papers. The topics discussed include: a zero-second-IF SiGe bicmos satellite radio tuner using a single PLL for both and IF LO generation and a replica ring-VCO calibrated IF Filter;high speed junction diodes in bicmos technologies;new electrothermal modeling tools for automotive powers circuits design optimization;analysis of electrothermal effects in bipolar current mirrors;electrothermal effects in bipolar differential pairs;physics-based scalable modeling of GaAs HBTs;high accuracy temperature bipolar modeling for demanding bandgap application;new method for oxide capacitance extraction;integration of a 5.5V BVceo SiGe HBT within a 200 GHz SiGe bicmos process flow;impact of layout and process on RF and analog performances of 3D Damascene MIM capacitors;and electrically programmable fuses for analog and mixed signal applications in silicon germanium bicmos technologies.
Base resistance extraction for small geometry, self aligned bipolar transistors has become more problematic as the other resistances and capacitances effecting the input impedance have become more significant and dist...
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ISBN:
(纸本)9781424485796
Base resistance extraction for small geometry, self aligned bipolar transistors has become more problematic as the other resistances and capacitances effecting the input impedance have become more significant and distributed. Following an introduction to Analog Devices' XFCB3 process, this paper will review a combination of measured results, TCAD simulations and Spice analysis of hybrid-pi equivalent circuits which were used to better understand the base resistance extraction issues.
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