An 850 mW SiGe power amplifier operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB of gain and 18% PAE is presented. This SiGe PA was implemented in a commercially-available, third-generation 130 nm 200 GHz...
详细信息
ISBN:
(纸本)9781424427253
An 850 mW SiGe power amplifier operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB of gain and 18% PAE is presented. This SiGe PA was implemented in a commercially-available, third-generation 130 nm 200 GHz SiGe bicmos platform using a hybrid high-breakdown / high-speed cascode pair to enhance voltage swing.
In this paper, we presents the design and implementation of a bicmos operational amplifier topology that operates from a 2.5V supply and achieves record gain-bandwidth performance. First, a fully-differential, single ...
详细信息
ISBN:
(纸本)9781424427253
In this paper, we presents the design and implementation of a bicmos operational amplifier topology that operates from a 2.5V supply and achieves record gain-bandwidth performance. First, a fully-differential, single stage folded-cascode with tunable common-mode feedback is described. In order to improve the DC gain of this circuit, a second version is implemented with differential gain boosting and achieves 48dB of gain while maintaining a unity gain bandwidth of 9GHz.
Footprint design in SiGe bicmos SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon o...
详细信息
ISBN:
(纸本)9781424427253
Footprint design in SiGe bicmos SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f(T) and noise figure improves slightly with footprint, and peak f(MAX) improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for bicmos devices on SOI is also proposed.
The third generation of NXP 0.25 mu m SiGe bicmostechnology (QUBiC4Xi) is presented. The NPN has f(T)/f(max) of 216/177 GHz and BVcb0 of 5.2 V. The high-voltage NPN has 12 V BVcb0, and f(T)/f(max) of 80/162 GHz. This...
详细信息
ISBN:
(纸本)9781424427253
The third generation of NXP 0.25 mu m SiGe bicmostechnology (QUBiC4Xi) is presented. The NPN has f(T)/f(max) of 216/177 GHz and BVcb0 of 5.2 V. The high-voltage NPN has 12 V BVcb0, and f(T)/f(max) of 80/162 GHz. This is complemented with an improved MIM capacitor with 1THz cutoff frequency and new on-chip isolation structures that demonstrate a record [S12] of -60 dB at 10 GHz.
Two MIM capacitors with capacitance density of 11 and 0.48 fF/um2 were fabricated simultaneously using IBM's 0.13um SiGe8WL bicmos process. Results from DC parametric measurement indicate that these two capacitors...
详细信息
ISBN:
(纸本)9781424427253
Two MIM capacitors with capacitance density of 11 and 0.48 fF/um2 were fabricated simultaneously using IBM's 0.13um SiGe8WL bicmos process. Results from DC parametric measurement indicate that these two capacitors compliment each other extremely well.
SiGe bipolar transistors with FT of 270 GHz are integrated within a standard 0.18 mu m CMOS process flow. These devices are built using the same architecture as Jazz' SBC18 SiGe bicmos process which has been in hi...
详细信息
ISBN:
(纸本)9781424427253
SiGe bipolar transistors with FT of 270 GHz are integrated within a standard 0.18 mu m CMOS process flow. These devices are built using the same architecture as Jazz' SBC18 SiGe bicmos process which has been in high-volume manufacturing for several years. The transistors have an F-MAX of 170 GHz but a path to achieving an F-MAX equal to FT is demonstrated without the use of selective SiGe epitaxy or raised extrinsic base poly layers. Data is shown that suggests that the target of 270 GHz F-MAX can be achieved through a combination of modest design rule changes and optimization of extrinsic base doping conditions.
Leakage through the base is a common yield detractor in SiGe NPNs. The defects are commonly referred to as 'pipes' and are manifested as a current path between emitter and collector independent of base bias. I...
详细信息
ISBN:
(纸本)9781424427253
Leakage through the base is a common yield detractor in SiGe NPNs. The defects are commonly referred to as 'pipes' and are manifested as a current path between emitter and collector independent of base bias. In this article we discuss pipes which have been observed due to retarded base growth. Advanced light /thermally induced voltage alterations (LIVA) and cross section transmission electron microscopy (XTEM) were used to identify these defects, which resulted in leakage paths through the base to the collector. The pipes were found to have resistances ranging 100-200 k Omega, and could be modeled as junction field-effect transistors (JFETs) in which the pipes serve as the channel and the base as the gate electrode. technology computer-aided design (TCAD) was utilized to model the pipes and provide insight into their behavior. In particular, the higher CE leakage currents of NPNs containing a selective collector implant are explained by changes in the conduction band resulting from the SIC implant. This correlates with observed NPN yield trends.
This paper describes a single-phase VCO followed by a polyphase filter to generate 60GHz quadrature signals. The IC is implemented in a SiGe:C-bicmos process. A quadrature down-conversion mixer is included for accurat...
详细信息
ISBN:
(纸本)9781424427253
This paper describes a single-phase VCO followed by a polyphase filter to generate 60GHz quadrature signals. The IC is implemented in a SiGe:C-bicmos process. A quadrature down-conversion mixer is included for accurate evaluation of I/Q-matching. The RF inputs of the mixers are driven via an on-chip passive power splitter. The VCO exhibits a tuning range between 59.5-61.5GHz and a phase noise of -92dBc/Hz at 1MHz offset from the carrier. The measured I/Q-matching of 28.6dB corresponds to a phase error of 4.2 degrees. The power consumption of the IC including the mixers is 150mW at a supply voltage of 4.5V and the chip area including bondpads is 1mm(2).
暂无评论