We demonstrate a 4-mask HBT module, which enables the integration of three high performance self-aligned SiGeC HBTs into a 0.13 mu m SOI CMOS technology. Static and dynamic transistor characteristics are described and...
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ISBN:
(纸本)0780393090
We demonstrate a 4-mask HBT module, which enables the integration of three high performance self-aligned SiGeC HBTs into a 0.13 mu m SOI CMOS technology. Static and dynamic transistor characteristics are described and compare with simulation results and bulk device performances.
This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-mn bicmostechnology. The technical choices such as the selective epitaxial growth of the base and the use of an a...
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This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-mn bicmostechnology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to bicmos performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.
A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-mu m SiGe bicmostechnology featuring 120 GHz f(T) and 100 GHz f(max) HBTs. It consists of ...
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A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-mu m SiGe bicmostechnology featuring 120 GHz f(T) and 100 GHz f(max) HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.
A SiGe limiting amplifier with 30dB gain, 16dB input return loss, 2mV sensitivity and integrated peak detect circuitry has been designed. The process used was a .13 micron bicmos graded base HBT technology. Peak detec...
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The cellular infrastructure market requires high clock rate, high dynamic range ADCs to enable efficient, advanced architecture receive channels. This paper describes a 14 bit 80MSPS ADC with 100dB+ SFDR at baseband i...
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ISBN:
(纸本)0780393090
The cellular infrastructure market requires high clock rate, high dynamic range ADCs to enable efficient, advanced architecture receive channels. This paper describes a 14 bit 80MSPS ADC with 100dB+ SFDR at baseband in 0.35um bicmostechnology using 1.1 watts on a 3.3V/5.0V dual supply. Some challenges associated with high spurious free dynamic range at high clock rates will be discussed along with methods used in this ADC to overcome these barriers.
We present a low-cost, modular bicmos process for wireless and mixed-signal applications. A SiGe:C bipolar module, a complementary LDMOS module, and a low-power flash memory were combined with a 0.25μm CMOS technolog...
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This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-mn bicmostechnology. The technical choices such as the selective epitaxial growth of the base and the use of an a...
详细信息
This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-mn bicmostechnology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to bicmos performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.
An injection-locked clock recovery (CR) unit capable of extracting the clock from random binary sequences is presented. At 2.3V, the clock recovery circuit consumes only 14.3mW and correctly recovers a 10.3GHz clock f...
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In this paper, a 5.8 GHz MMIC down-conversion mixers are designed and fabricated on chip using SiGe bicmos process technology. To fabricate a SiGe HBT, we use a RPCVD system to grow a base epitaxial layer, and have ad...
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This paper presents a superheterodyne down-converter realized using SiGe:C bicmos HBT. Based on a single-ended architecture, the Low Noise Amplifier (LNA), the fundamental oscillator and the mixer were first character...
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