This paper examines the feasibility of implementing transmission lines in a commercially-available SiGe HBT bicmostechnology. Thin film microstrip transmission lines, using the top and bottom metalization layers (wit...
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This paper examines the feasibility of implementing transmission lines in a commercially-available SiGe HBT bicmostechnology. Thin film microstrip transmission lines, using the top and bottom metalization layers (with a 3.24 /spl mu/m separation), from a 4 layer metal process SiGe HBT technology were designed, fabricated, and measured up to 110 GHz. These measured results were compared to full wave EM simulation results to gain additional design insight. Additional EM simulations were used to explore the effects of design rule changes which do not allow for large extents of ground plane without slotting.
We use full 3D EM simulation to optimize the design of a 30 GHz branch line coupler using thin film microstrip lines (TFMS) in a commercial 120 GHz SiGe HBT bicmostechnology. The effects of various ground plane conne...
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We use full 3D EM simulation to optimize the design of a 30 GHz branch line coupler using thin film microstrip lines (TFMS) in a commercial 120 GHz SiGe HBT bicmostechnology. The effects of various ground plane connections are considered for designing the branch line coupler. With an improper design of the ground plane in the TFMS, the measured S/sub 21/ shows 7 dB degradation at 30 GHz, in agreement with simulation. A carefully optimized coupler design shows that -4 dB S/sub 21//S/sub 31/ with -15 dB reflection coefficient at 30 GHz should be achievable.
The "tanh" ideal and lossy ELIN (externally linear, internally nonlinear) integrators as basic building blocks for active filter design are studied. The circuits have been obtained using state-space synthesi...
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The "tanh" ideal and lossy ELIN (externally linear, internally nonlinear) integrators as basic building blocks for active filter design are studied. The circuits have been obtained using state-space synthesis and are composed of "tanh" and "sinh/cosh" blocks which can be implemented in bipolartechnology. It is shown that a "tanh" ideal ELIN integrator is difficult to use in practice because an appropriate dc equilibrium does not exist. Thus, for the working of such an ELIN system, which realizes the ideal integrator's transfer characteristic, the input dc level must be zero. The problems of dc and low frequency operation can be eliminated by using the "tanh" lossy ELIN integrator. The linearity range of the proposed structure depends on the accuracy in which the range of the "tanh" transfer characteristics is valid, this being limited (from the existing condition of the input inverse function, "arctanh") to the bias current value. Also studied is the unbalance effect of the two bias currents of the nonlinear "tanh" transconductance on the "tanh" lossy ELIN integrator in dc and ac operation. Finally, the core layout of the "tanh" lossy ELIN integrator in 0.8 /spl mu/m bicmostechnology is presented. The proposed circuit has been simulated in 0.8 /spl mu/m bicmostechnology showing remarkably good performance, and proving the practical applicability of the proposed structure.
A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs o...
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A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs on silicon islands in the BOX. Low-resistance collector wells are realized by ion implantation into the SOI substrate. SiGe:C HBTs with f/sub T//f/sub max/ values of 220 GHz/230 GHz and a BV/sub CEO/ of 2.0 V and fully-depleted CMOS transistors with 90 nm gate length are fabricated on SOI wafers with 30 nm Si thickness.
The proceedings contains 40 papers from the conference of the 2001 bipolar/bicmos circuits and technology meeting. Topics discussed include: prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistor...
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The proceedings contains 40 papers from the conference of the 2001 bipolar/bicmos circuits and technology meeting. Topics discussed include: prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors;an accurate transistor model for simulating avalanche-breakdown effects in Si bipolarcircuits;ultra shallow boron base profile with carbon implantation;architecture and technology for multistandard transceivers;polar modulators for 1 and 2 GHz power amplifier correction;analog design in the information age;and silicon carbide devices for power applications.
The undesired influence of the substrate on circuit performance cannot be neglected for many advanced high-speed and RF circuits and must therefore be modeled correctly already in the design phase. This paper gives an...
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ISBN:
(纸本)0780378008
The undesired influence of the substrate on circuit performance cannot be neglected for many advanced high-speed and RF circuits and must therefore be modeled correctly already in the design phase. This paper gives an overview of the interaction between circuit components and the substrate and reviews simulation techniques that can be used to determine its influence. In addition, the integration of substrate modeling into today's design environments will be discussed and explained by a practical example.
A master-slave latch and companion 1:2, 1:4 and 1:8 static frequency dividers fabricated in 120GHz f(T) SiGe operate at 51GHz, while drawing 30 mA per latch (780mA total, with input-output buffers) from a -5.2V power ...
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ISBN:
(纸本)0780378008
A master-slave latch and companion 1:2, 1:4 and 1:8 static frequency dividers fabricated in 120GHz f(T) SiGe operate at 51GHz, while drawing 30 mA per latch (780mA total, with input-output buffers) from a -5.2V power supply. At 40Gb/s (40GHz clock) latch operates error-free (BER better than 10-(14), 2(31)-1 PRBS) with 152degrees data-clock phase margin. The directly observed width of the metastability zone of the latch is 1.2ps.
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