A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The ...
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A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a by-passable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.
The undesired influence of the substrate on circuit performance cannot be neglected for many advanced high-speed and RF circuits and must therefore be modelled correctly already in the design phase. This paper gives a...
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The undesired influence of the substrate on circuit performance cannot be neglected for many advanced high-speed and RF circuits and must therefore be modelled correctly already in the design phase. This paper gives an overview of the interaction between circuit components and the substrate and reviews simulation techniques that can be used to determine its influence. In addition, the integration of substrate modelling into today's design environments will be discussed and explained by a practical example.
A low-voltage static 1:2 divider using CML gates with a single-transistor switching stack was designed in a 0.18 /spl mu/m SiGe bicmostechnology. The divider operates at 11 GHz from 1.0V supply and 16.2 GHz from 1.4 ...
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A low-voltage static 1:2 divider using CML gates with a single-transistor switching stack was designed in a 0.18 /spl mu/m SiGe bicmostechnology. The divider operates at 11 GHz from 1.0V supply and 16.2 GHz from 1.4 V supply.
A novel approach for the ESD protection of analog circuits using a pad-to-pad network is proposed and validated by numerical simulation and experimental data. The network is formed by inter-linked bi-directional SCR...
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A novel approach for the ESD protection of analog circuits using a pad-to-pad network is proposed and validated by numerical simulation and experimental data. The network is formed by inter-linked bi-directional SCR's. This network provides a space saving solution to the requirement for providing ESD protection for arbitrary pin-to-pin combinations, and is especially attractive for small analog circuits in bipolar and bicmos technologies.
Why and how can parametric mismatch studies help to improve IC-technologies? After an introduction on the importance of parametric mismatch for performance and yield of mixed-signal as well as digital technologies, th...
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Why and how can parametric mismatch studies help to improve IC-technologies? After an introduction on the importance of parametric mismatch for performance and yield of mixed-signal as well as digital technologies, the basic terminology and techniques for BJT mismatch fluctuation assessment are reviewed. Two examples are discussed to demonstrate how parametric mismatch fluctuation studies help to improve better device architecture of poly-emitter BJTs. The ensuing process refinements result in better circuit functionality as well as yield improvements.
This paper describes ST new bicmos RF technology based on a mature 0.25/spl mu/m CMOS process. Two SiGe:C HBTs are implemented for low and high voltage applications. Very low noise figure of 0.4dB at 2GHz is achieved....
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This paper describes ST new bicmos RF technology based on a mature 0.25/spl mu/m CMOS process. Two SiGe:C HBTs are implemented for low and high voltage applications. Very low noise figure of 0.4dB at 2GHz is achieved. Other devices like isolated vertical PNP BJT, NLDEMOS and advanced passives are integrated in this technology to address RF circuit needs.
A novel complementary-SiGe bicmostechnology developed for ultra-high speed precision analog circuits is presented. The modular process offers comparable NPN and PNP performance utilizing unique interface and SiGe bas...
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A novel complementary-SiGe bicmostechnology developed for ultra-high speed precision analog circuits is presented. The modular process offers comparable NPN and PNP performance utilizing unique interface and SiGe base process.
A fully integrated rf power amplifier for 7-18 GHz-f/sub T/ with no external components was realized in a 75GHz-f/sub T/, 0.35/spl mu/m-SiGe-bicmostechnology. At 17.2GHz the push-pull amplifier with integrated output...
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A fully integrated rf power amplifier for 7-18 GHz-f/sub T/ with no external components was realized in a 75GHz-f/sub T/, 0.35/spl mu/m-SiGe-bicmostechnology. At 17.2GHz the push-pull amplifier with integrated output balun delivers 12dBm, 17.5 dBm at 1.2V, 2.4V.
This paper describes a manufacturable 0.13/spl mu/m SiGe:C bicmostechnology for optical networking and wireless applications, with npn f/sub T//f/sub max/ of 166/175GHz and 1.8V BV/sub CEO/, dual V/sub T/ and dual ga...
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This paper describes a manufacturable 0.13/spl mu/m SiGe:C bicmostechnology for optical networking and wireless applications, with npn f/sub T//f/sub max/ of 166/175GHz and 1.8V BV/sub CEO/, dual V/sub T/ and dual gate oxide CMOS devices, high quality passives and a 6-level copper back-end.
A balanced low noise amplifier (LNA) has been integrated in a 0.25/spl mu/m bicmostechnology. To reduce power consumption and improve performances, two stages that share the same DC current have been stacked. A Mille...
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A balanced low noise amplifier (LNA) has been integrated in a 0.25/spl mu/m bicmostechnology. To reduce power consumption and improve performances, two stages that share the same DC current have been stacked. A Miller effect neutralization scheme avoids the need to cascode transistors. The LNA takes an area of 0.8 /spl times/ 1.15 mm/sup 2/ (bondwire pads excluded) and draws 14.4mW from a 1.8V supply voltage. In this conditions, measured parameters at 8.2-GHz are NF=1.6dB, power gain Gp=22-dB, output P1dB=3.3dBm at 8.2-GHz.
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