bicmos6G, a 200 mm 0.35 /spl mu/m SiGe bicmostechnology, is presented. This technology features a low complexity double-poly SiGe HBT with 60 GHz f/sub max/, added to stand-alone CMOS and high-quality passive compone...
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bicmos6G, a 200 mm 0.35 /spl mu/m SiGe bicmostechnology, is presented. This technology features a low complexity double-poly SiGe HBT with 60 GHz f/sub max/, added to stand-alone CMOS and high-quality passive components. It is ideally suited to the development of highly integrated wireless communications circuits.
We report a new super self-aligned graded SiGe base transistor that uses high energy implantation, rather than epitaxial growth, to form the sub-collector region. This new inexpensive process yields a device with fT o...
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We report a new super self-aligned graded SiGe base transistor that uses high energy implantation, rather than epitaxial growth, to form the sub-collector region. This new inexpensive process yields a device with fT of 52 GHz and fmax of 70 GHz with the addition of only 4 lithography levels over our 0.25 μm CMOS technology without any changes to the existing process steps. Also, we demonstrate 4:1 multiplexer and 1:4 demultiplexer circuits using this technology that show excellent performance at 10 Gbit/s.
A review of bicmos modeling from a RF designer's point of view is presented, Pitfalls of standard models are shown in the context of modern device design. A few circuit examples are presented to illustrate the imp...
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A review of bicmos modeling from a RF designer's point of view is presented, Pitfalls of standard models are shown in the context of modern device design. A few circuit examples are presented to illustrate the impact of device modeling on RF IC design.
Design of a compact square-cell, dual-direction ESD protection structure for bicmos ICs is reported. Detailed design features, such as, improved current uniformity, high-ESD protection level (>14 kV HBM), high-ESDV...
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ISBN:
(纸本)0780357132
Design of a compact square-cell, dual-direction ESD protection structure for bicmos ICs is reported. Detailed design features, such as, improved current uniformity, high-ESD protection level (>14 kV HBM), high-ESDV/Si ratio (/spl sim/1.66 V//spl mu/m/sup 2/), and adjustable trigger voltage are discussed.
In a cellular radio, as in any system, the architecture determines the quantity and quality of bipolar and bicmos content. Requirements and merits of a few transmitter and receiver architectures are discussed. Some of...
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In a cellular radio, as in any system, the architecture determines the quantity and quality of bipolar and bicmos content. Requirements and merits of a few transmitter and receiver architectures are discussed. Some of these, such as single IF, are in handsets selling by the millions every year. Some, such as direct conversion at the antenna, remain in the planning stages because of the present state of A/D technology.
Design tradeoffs for the optimization of inductor Q have been analyzed, and thick metallization has been identified as the most promising technology enhancement. Peak Qs approaching 19 have been demonstrated using thi...
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Design tradeoffs for the optimization of inductor Q have been analyzed, and thick metallization has been identified as the most promising technology enhancement. Peak Qs approaching 19 have been demonstrated using thick metal.
This paper presents a 20-channel, 4.850-5.325 GHz PLL-based frequency synthesizer implemented in a production SiGe bicmostechnology. The circuit is fully integrated, including the loop filter capacitor and VCO. A fas...
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This paper presents a 20-channel, 4.850-5.325 GHz PLL-based frequency synthesizer implemented in a production SiGe bicmostechnology. The circuit is fully integrated, including the loop filter capacitor and VCO. A fast settling time of 10 /spl mu/s is measured with a reference frequency of 12.5 MHz. Wafer-level tests indicate a phase noise below -100 dBc/Hz at a 1 MHz offset. The chip dissipates 255 mW from a 3.3 V supply and occupies an active area of 2 mm/sup 2/.
In order to fully integrate a low power, low phase noise frequency synthesizer, a 2.3 GHz synchronous oscillator has been fully implemented on a 0.8 /spl mu/m, two metal layer standard bicmostechnology. It is able to...
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In order to fully integrate a low power, low phase noise frequency synthesizer, a 2.3 GHz synchronous oscillator has been fully implemented on a 0.8 /spl mu/m, two metal layer standard bicmostechnology. It is able to lock on a subharmonic external signal and its locking range is about 40 MHz for a 400 MHz injected signal. The oscillator and its synchronization circuit consume less than 14 mA on a 3 V battery.
Using a newly proposed structure of the multi-via MIM capacitor, amorphous Ta/sub 2/O/sub 5/ films were investigated. Amorphous Ta/sub 2/O/sub 5/ with the proposed structure is one of the suitable combinations for the...
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Using a newly proposed structure of the multi-via MIM capacitor, amorphous Ta/sub 2/O/sub 5/ films were investigated. Amorphous Ta/sub 2/O/sub 5/ with the proposed structure is one of the suitable combinations for the capacitors for RF analog applications.
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