A minicomputer-controlled electron beam recorder (EBR) presently in use at the brazilian Government's Institute De Pesquisas Espaclais (INPE) satellite ground station is described. This 5-in-film-size EBR is used ...
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A minicomputer-controlled electron beam recorder (EBR) presently in use at the brazilian Government's Institute De Pesquisas Espaclais (INPE) satellite ground station is described. This 5-in-film-size EBR is used to record both Landsat and SPOT satellite imagery in South America. A brief electron beam recorder technology review is presented. The EBR is capable of recording both vector and text data from computer-aided design, publishing, and line art systems and raster data from image scanners, raster image processors (RIPS), halftone/screen generators, and remote image sensors. A variety of image formats may be recorded on numerous film sizes (16 mm, 35 mm, 70 mm, 105 mm, 5-in, 5-1/2-in, and 9-1/2-in). These recordings are used directly or optically enlarged depending on the final product.
A radar stereopair over Montagne-Sainte-Victoire (southern France) was chosen in order to test the suitability of the Varan-S data for a radargrammetric application. Radar stereomapping software was used at the Instit...
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A radar stereopair over Montagne-Sainte-Victoire (southern France) was chosen in order to test the suitability of the Varan-S data for a radargrammetric application. Radar stereomapping software was used at the Institute of imageprocessing and computergraphics (Graz, Austria) to provide a DEM (digital elevation model) of the test site. The study showed that the Varan-S data are suitable for a radargrammetric application unless they display undue distortions.
A novel method that provides extremely fast Input/Output (I/O) data transfer to a RISC-like graphics engine is presented. This method employs a combined two-port / two-access and a three-port / three-access register f...
ISBN:
(纸本)9780897913195
A novel method that provides extremely fast Input/Output (I/O) data transfer to a RISC-like graphics engine is presented. This method employs a combined two-port / two-access and a three-port / three-access register file used for concurrent processing and I/O data transfer. The three-port cell employed is only 25 % larger than the two-port cell, offering considerable advantages over alternative approaches, such as FIFOs or register *** paper discusses some methods that can provide highly fast I/O data transfer in parallel with execution and focuses on the design and implementation of the CMOS-2um register file *** Terms - computer Architecture, Reduced Instruction Set computers, VLSI Design, computerimage Generation, Interprocessor Communication.
RIG is a fast Reduced Instruction Set Processor suitable for Real-Time image Generation (RTIG) Geometric Computations. It is designed to be used in a parallel processing architecture, so that high polygon throughput c...
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RIG is a fast Reduced Instruction Set Processor suitable for Real-Time image Generation (RTIG) Geometric Computations. It is designed to be used in a parallel processing architecture, so that high polygon throughput can be achieved. RIG is a 16 MIPS processor that can execute the geometric computations required in RTIG at least ten times faster than a MC68000-12Mhz microprocessor due to the following innovations and characteristics: ?? A novel “Data Ready” technique, in which data is available without waiting for external memory. Data is transferred in burst mode (via DMA) directly into processor internal registers in parallel with processing.
?? “Indices” to the General-Purpose Registers instead of “Register Windows” schemes, as a fast and efficient parameter passing mechanism in procedure calls.
?? Fast multiplication and division instructions together with a three-staged pipeline architecture with “data forwarding”.
?? Extremely fast interaction with a parallel processing system with minimum overhead.
It is demonstrated that with a modicum of compilation complexity a scan line array processor (SLAP) (a single-instruction multiple-data (SIMD) architecture designed for image computation and similar applications) beco...
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It is demonstrated that with a modicum of compilation complexity a scan line array processor (SLAP) (a single-instruction multiple-data (SIMD) architecture designed for image computation and similar applications) becomes a versatile tool, efficiently supporting a number of useful programming models: position-independent (low-level image-processing operations), scan-line (intermediate-level imageprocessing and graphics), and systolic. The impact of programming issues on overall system architecutre is discussed with respect to hierarchical control structures, the handling of concurrent I/O streams, and the importance of considering whole applications. Such considerations are critical to the success of highly parallel systems, particularly those designed for imbedded applications, yet often are treated as afterthoughts. The high-level SLAP programming language Slang is introduced.
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