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检索条件"任意字段=CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems"

共 381 条记录，以下是111-120 订阅

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Towards automatic synthesis of a class of application-specific sensor networks

Towards automatic synthesis of a class of application-specif...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Bakshi, Amol Ou, Jingzhao Prasanna, Viktor K. Dept. of EE-Systems University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)1581135750

Automatic synthesis of sensor network-based systems can be described as the process of translating a formal specification of application functionality into a particular task mapping, settings of available hardware knobs, and communication and coordination mechanisms among the sensor nodes, so as to meet the performance requirements and constraints. We propose a general methodology to tackle a specific class of this problem, based on analytical performance modeling, multigranularity system simulation, and automatic refinement of model parameters. To demonstrate the utility and feasibility of our proposed methodology, we define a system model for a class of sensor networks, and implement a software framework for its modeling and simulation. Our graphical design environment supports plug-and-play integration of different performance models, simulation and visualization suites, and even automatic design space exploration and optimization tools. Copyright 2002 ACM.

关键词： Energy efficiency

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Balancing and context-switching in ASTI systems

Balancing and context-switching in ASTI systems

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cases 2005: international conference on compilers, architecture, and synthesis for embedded systems

作者： Shivshankar, Siddhartha Vangara, Sunil Dean, Alexander G. Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University Raleigh NC United States

ISBN: (纸本)159593149X

This paper makes two contributions to Asynchronous Software Thread Integration (ASTI). First, it presents methods to calculate worst-case secondary thread performance statically. This will enable real-time performance guarantees for the system in future work. Second, it improves the run-time performance of integrated threads by partitioning the register file, allowing faster coroutine calls. Determining the ideal partitioning of the register file is non-trivial if the registers are heterogeneous, which is a common case. We use an exhaustive search to explore the limits of performance possible. We have implemented these analyses in our research compiler Thrint and a shell script to create an automated system for design space exploration. We present experimental results showing the secondary thread performance attainable on an 8-bit embedded microcontroller of the AYR architecture. We automatically integrate two embedded protocols (CAN and MIL-STD-1553B) and two secondary threads (PID controller and serial host interface) and find that in most cases the AVR's 32 registers are adequate for both threads with no slowdown. In two cases slowdowns reach 1.8%, a negligible penalty. Copyright 2005 ACM.

关键词： Real time systems

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Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips

Tabu search-based synthesis of dynamically reconfigurable di...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Maftei, Elena Pop, Paul Madsen, Jan DTU Informatics Technical University of Denmark DK-2800 Kgs. Lyngby Denmark

ISBN: (纸本)9781605586267

Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. The "digital" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets, and hence they are highly reconfigurable and scalable. A digital biochip is composed of a two-dimensional array of cells, together with reservoirs for storing the samples and reagents. Several adjacent cells are dynamically grouped to form a virtual device, on which operations are executed. During the execution of an operation, the virtual device can be reconfigured to occupy a different group of cells on the array. In this paper, we present a Tabu Search metaheuristic for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determines the allocation, resource binding, scheduling and placement of the operations in the application. In our approach, we consider moving the modules during their operation, in order to improve the completion time of the biochemical application. The proposed heuristic has been evaluated using three real-life case studies and ten synthetic benchmarks. Copyright 2009 ACM.

关键词： Tabu search

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A prototype network embedded in textile fabric 2

A prototype network embedded in textile fabric

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2nd international conference on compilers, architecture, and synthesis for embedded systems, cases 2001

作者： Mackenzie, Kenneth Hudson, Eric Maule, Drew Jayaraman, Sundaresan Park, Sungmee College of Computing Georgia Institute of Technology AtlantaGA30332 United States School of Textile and Fiber Engineering Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)1581133995

A digital network between active components or "buttons" atop an e-textile fabric must handle the inexact placement of wires in the fabric both for signal distribution and for power distribution. We approach the problem of signal distribution by making the pin logic of the buttons reconfigurable and by providing enough local state to allow an external agent to discover and to reconfigure the buttons into a working network. We describe a prototype system of a 2x2 array of FPGAand- microcontroller buttons atop a fabric with 0.100"-pitch wiring including architecture decisions, circuits and software algorithms. Copyright 2001 ACM.

关键词： Textiles

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Dynamic battery state aware approaches for improving battery utilization

Dynamic battery state aware approaches for improving battery...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Park, Sung Srivastava, Mani B. Networked and Embedded Systems Lab. Electrical Engineering Department UCLA Los Angeles CA 90095 United States

ISBN: (纸本)1581135750

In this paper we introduce novel battery state aware strategies that improve the performance of battery operated systems. In our analysis, we consider the total amount of work done (or service) as the metric instead of considering just the lifetime. Based on our analysis using service curves, we formulate our static approach which generalizes many of the battery aware approaches introduced in the literatures. The results show that the static approach increases the battery utilization by 600% over a non battery aware approach. Furthermore, we show that our dynamic battery state aware approach improves upon the static approach by dynamically adapting the system performance level based on batteryes voltage slope. The results indicate that the dynamic approach achieves improvement of up to 20% over the static approach. Copyright 2002 ACM.

关键词： Electric batteries

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Real Java for real time - Gain and pain

Real Java for real time - Gain and pain

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Nilsson, Anders Ekman, Torbjörn Nilsson, Klas Dept. of Computer Science Lund University Box 118 S-221 00 Sweden

ISBN: (纸本)1581135750

The Java programming language, being a portable and safe object-oriented language, has gained much interest among embedded and real-time systems developers. However, standard Java implementations exhibit problems with performance, memory footprint, and predictability. The question is then, are these limitations inherent in the technology? Reviewing run-time aspects and the possibility to compile Java to native code, reveals some real limitations as well as common misconceptions. Investigation of the real limitations shows that for implementing real-time Java on small embedded platforms, native compilation via C is an appropriate solution for many platforms and applications. A revised technique for Java-compatible memory management is proposed to reduce latencies, and linkage of externally generated (C) code with natively compiled Java is considered in a prototype that has been implemented. Based on application demands and experimental verification, we find that real-time Java can, and should, retain the standard simple Java memory model to the programmer. Copyright 2002 ACM.

关键词： embedded systems

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From Sequential Programming to Flexible Parallel Execution

From Sequential Programming to Flexible Parallel Execution

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ACM international conference on compilers, architectures and synthesis for embedded systems (cases)

作者： Raman, Arun Lee, Jae W. August, David I. Intel Labs Santa Clara CA USA

ISBN: (纸本)9781450314244

The embedded computing landscape is being transformed by three trends: growing demand for greater functionality and enriched user experience, increasing diversity and parallelism in the processing substrate, and an accelerating push for ever-greater energy efficiency. For programmers, these trends give rise to three challenges: writing code for a potentially heterogeneous architecture, extracting parallelism in software, and maximizing a multivariate (performance, power, energy, etc.) fitness function of user satisfaction which may vary with time. To meet these challenges, clarion calls have been issued for programmers to start writing software in new parallel programming models. Fundamentally, however, these proposals detract programmers from delivering new features and enriched user experience in the shortest time possible. This paper proposes to attract embedded systems programmers to a vertically integrated approach, comprising extensions to the sequential programming model, a parallelizing compiler, and an optimizing run-time system, to enable them to tackle all three challenges.

关键词： adaptivity code generation compiler embedded flexible GPGPU heterogeneous multicore optimization parallel parallelization performance portability run-time tuning

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Frequent loop detection using efficient non-intrusive on-chip hardware

Frequent loop detection using efficient non-intrusive on-chi...

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cases 2003: international conference on compilers, architecture, and synthesis for embedded systems

作者： Gordon-Ross, Ann Vahid, Frank Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States

ISBN: (纸本)1581136765

Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting frequently executed code, or "critical regions." Previous critical region detectors have been targeted to desktop processors. We introduce a critical region detector targeted to embedded processors, with the unique features of being very size and power efficient, and being completely non-intrusive to the software's execution - features needed in timing-sensitive embedded systems. Our detector not only finds the critical regions, but also determines their relative frequencies, a potentially important feature for selecting among alternative dynamic optimization methods. Our detector uses a tiny cache coupled with a small amount of logic. We provide results of extensive explorations across seventeen embedded system benchmarks. We show that highly accurate results can be achieved with only a 0.02% power overhead and acceptable size overhead. Our detector is currently being used as part of a dynamic hardware/software partitioning approach, but is applicable to a wide-variety of situations. Copyright 2003 ACM.

关键词： embedded systems

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Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions

Reducing impact of cache miss stalls in embedded systems by ...

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embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on compilers, architecture, and synthesis for embedded systems, cases'09

作者： Bournoutian, Garo Orailoglu, Alex University of California San Diego 9500 Gilman Dr. #0404 San Diego CA 92093-0404 United States

ISBN: (纸本)9781605586267

Today, embedded processors are expected to be able to run complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. As such, the impact of memory latencies on the execution time increasingly becomes evident. All the while, it is also expected that embedded processors be power-conscientious as well as of minimal area impact. As a result, traditional methods for addressing performance and memory latencies, such as multiple issue, out-of-order execution and large, associative caches, are not aptly suited for the embedded domain due to the significant area and power overhead. This paper explores a novel approach to mitigating execution delays caused by memory latencies that would otherwise not be possible in a regular in-order, single-issue embedded processor without large, power-hungry constructs like a Reorder Buffer (ROB). The concept relies on both compile-time and run-time information to safely allow non-data-dependent instructions to continue executing while a memory stall has occurred. The simulation results show significant improvement in execution throughput of approximately 11%, while having a minimal impact on area overhead and power. Copyright 2009 ACM.

关键词： embedded systems

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On achieving balanced power consumption in software pipelined loops

On achieving balanced power consumption in software pipeline...

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2002 international conference on compilers, architecture, and synthesis for embedded systems, cases '02

作者： Yang, Hongbo Gao, Guang R. Leung, Clement Dept. of ECE University of Delaware Newark DE 19716 United States

ISBN: (纸本)1581135750

While a significant body of work in compilers has been devoted to reducing energy consumption in embedded systems, the role of a compiler in harnessing the power variation has not been widely explored. Since sharp power variations across time steps cause power supply noises and degrade reliability of functional blocks, power variation is a design constraint in embedded systems. With the advent of high performance embedded systems and extensive deployment of fine grain clock-gating, reducing variations in power is becoming increasingly important. This paper studies how compilation techniques, more specifically instruction scheduling, can ameliorate variations in power due to functional units during program execution. By extending our previous work on rate-optimal software pipelining, this paper formulates the problem of constructing a performance-optimal schedule that minimizes power variations as an integer linear programming (ILP) problem. The formulation can be solved using an ILP solver. We applied our approach on SPEC NAS benchmarks to construct software pipelined schedules that have minimum power variations. The benchmarks are executed on the Wattch power simulator. In comparison to the original (power-unaware) scheduler implemented in the MIPSpro compiler, our power-aware approach generates schedules which have significantly lower power variations while maintaining the same performance. Such schedules have the potential to reduce hardware cost on power delivery in designing embedded systems. Copyright 2002 ACM.

关键词： embedded systems

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